How can I get the MMC timing spec higher than sd high-speed?

[Tomáš Juřena]

Hello,

I am having difficulties with the MMC bus and the external SDIO wifi module. We are using the wifi module jody-w263 from U-blox with the OSD32MP1, and the communication with the module works, but it is quite slow. The wifi module is capable of SDR 104 and DDR50 communication speeds, but I add the support to the DTS, the communication is broken and the device returns the -110 while initializing.

How can I add support for higher speeds?

I attach the working dts, dmesg, ios and caps, and relevant schematic.

Any suggestion will be appreciated.

Best regards,

Tomáš.

[Olivier GALLIEN]

Hi @Tom�? Ju?ena​ ,

Sorry for late reply.

Where do you stand regarding this question ?

Looking at provided material we noticed 1 things as first hints :

• you wifi module is powered @1.8V but we notice in dts "vmmc-supply = <&v3v3>;"

This assumption is confirmed by dmesg trace which complain about power issues :

[ 3.127353] mmci-pl18x 48004000.sdmmc: allocated mmc-pwrseq

[ 3.131985] mmci-pl18x 48004000.sdmmc: mmc0: PL180 manf 53 rev1 at 0x48004000 irq 30,0 (pio)

[ 3.140299] v1v8_ldo1: voltage operation not allowed

[ 3.144886] mmci-pl18x 48004000.sdmmc: Voltage switch failed

[ 3.160524] mmci-pl18x 48004000.sdmmc: Voltage switch failed

[ 3.164764] v1v8_ldo1: voltage operation not allowed

[ 3.169671] mmci-pl18x 48004000.sdmmc: Voltage switch failed

[ 3.203258] mmci-pl18x 58007000.sdmmc: mmc1: PL180 manf 53 rev2 at 0x58007000 irq 36,0 (pio)

[ 3.212309] vdd: voltage operation not allowed

[ 3.215352] mmci-pl18x 58007000.sdmmc: Voltage switch failed

[ 3.230984] mmci-pl18x 58007000.sdmmc: Voltage switch failed

[ 3.235253] vdd: voltage operation not allowed

[ 3.239630] mmci-pl18x 58007000.sdmmc: Voltage switch failed

[ 3.264593] mmc0: new high speed SDIO card at address 0001

Let us know

Olivier

[Tomáš Juřena]

Hi Oliver,

thanks for the reply.

We tried to set the 1.8 V regulator to the vmmc-supply before, but the module was not recognized. Is this crucial? We assumed that the vqmmc-supply is the regulator, that we need to configure to have the higher speeds.

[PatrickF]

Hi,

did you use a level translator for the 1.8V wifi signals or the OSD32MP1 IOs are at 1.8V ?

When you mention 'quite slow', could you please precise, because classical SDIO high-speed should already provide a raw bandwidth of 25MB/s (200Mbit/s).

DDR50 could provide raw bandwidth of 50MB/s (400 Mbits/s)

SDR50 and SDR104 are not usable (see ES438).

Mybe your PLL root clock settings are limiting the choice done by the Linux driver. See this FAQ: https://community.st.com/s/article/FAQ-STM32MP1-how-to-setup-the-SDMMC-CK-clock-frequency-in-Linux

Regards,

[PatrickF]

looking again at you zip file, I see

clock:          50000000 Hz
actual clock:   50000000 Hz
vdd:            21 (3.3 ~ 3.4 V)
bus mode:       2 (push-pull)
chip select:    0 (don't care)
power mode:     2 (on)
bus width:      2 (4 bits)
timing spec:    2 (sd high-speed)
signal voltage: 0 (3.30 V)
driver type:    0 (driver type B) 

as for using DDR50, the driver need to use at least a divider by 2 inside SDMMC, IP need to get 100MHz from the RCC. Maybe adapt your PLL post divider or SDMMC clock source.

Don't know if this would be enough to get DDR50 working, but it is a prerequisite.

Regards.

[Tomáš Juřena]

Hello Patrick,

yes, we have 1.8 V for IOs (vdd regulator on buck3 with fixed 1.8 V in DTS).

By slow, I meant the speed around 2MB/s. With CPU from NXP we were able to reach 4.5MB/s but with 3.3 V logic and level shifter to 1.8V (the fixed bus voltage on Jody-w2). The communication frequency was limited to ~22MHz (on ST we have 50MHz).

We are experimenting with configuration now and we noticed, that the setting regulator to 1.8 V returns ETIMEDOUT. Could this be related?

[    3.193435] mmci-pl18x 48004000.sdmmc: mmc0: PL180 manf 53 rev1 at 0x48004000 irq 40,0 (pio)
[    3.201209] mmci-pl18x 48004000.sdmmc: DMA is setup
[    3.206425] mmci-pl18x 48004000.sdmmc: mmc_set_initial_signal_voltage called
[    3.213115] mmci-pl18x 48004000.sdmmc: Switching voltage: 0
[    3.218749] mmci-pl18x 48004000.sdmmc: Request output voltage of vqmmc: 0
[    3.225490] v1v8_ldo1: voltage operation not allowed
[    3.230419] mmci-pl18x 48004000.sdmmc: Voltage switch failed. Exit code:-1
[    3.237313] mmci-pl18x 48004000.sdmmc: Switching voltage: 1
[    3.242849] mmci-pl18x 48004000.sdmmc: Request output voltage of vqmmc: 1
[    3.259694] mmci-pl18x 48004000.sdmmc: Voltage switch failed. Exit code:-110
[    3.265322] mmci-pl18x 48004000.sdmmc: Switching voltage: 2
[    3.270843] mmci-pl18x 48004000.sdmmc: Request output voltage of vqmmc: 2
[    3.277649] v1v8_ldo1: voltage operation not allowed
[    3.282580] mmci-pl18x 48004000.sdmmc: Voltage switch failed. Exit code:-1

[Tomáš Juřena]

Our clock tree is configured like this:I think this should be correct. Isn't it? Should I alter the SDMMC clock source? Can you guide me if so, please?

Best regards,

Tomáš.

[PatrickF]

Hi,

Apart the SDIO interface speed which does not reach DDR50 on your case, I escalated the WLAN network speed limitation issue internally in order to understand if the 2MB/s come from any setup in our SW (as on STM32MP157F-DK2 with Murata WLAN module, I also found 2MB/s uplink and 3.5MB/s downlink using iperf3).

Keep you posted.

Regards.

[Tomáš Juřena]

Hi Patrick,

by any chance, do you have updates on this issue?

Best wishes,

Tomáš.

[PatrickF]

Hi,

unfortunately, development team is busy on (many) other subjects.

We understand your concern, but as it is not blocking, some topics will got higher-priority. I don't have any provisional date for feedback.

Some contacts has been started with Murata (module maker for WLAN/BT on STM32MP157F-DK2) to help us to understand why we have this limitation in our board, but it will take time.

Regards.