CCM in stm32mp157

[AMART.1]

Hi all,

If I dedicate the MCU SRAM2 for data and MCU SRAM4 for DMA as shown here, do I get CCM like performance or do I have a risk to have contention on the SRAM2 ?

After looking at the bus matrix, I suspect there is no risk but I want to make sure it is the case.

[PatrickF · Accepted solution]

I confirm there is no contention in the MLAHB matrix, e.g. in your case between Cortex-M4 and SRAM2 and DMA access to SRAM4.

For information, to get best performances for Cortex-M4 DATA access, either RETRAM (@0x00000000, using D-Bus) or SRAM2 alias (@0x30020000, using S-Bus) should be used (other SRAMs have still good performances, but could have 1 additional wait-state on non-sequential access from Cortex-M4). Notice that Cortex-M4 INSTRUCTION fetch is 'optimized' on either S-bus or I-bus on all SRAMs and RETRAM (even if I-bus should be preferable).

[AMART.1]

Hi @PatrickF​ ,

Thanks for the detailed explanation.