What is the correct Linux pin control configuration for ANA0 and ANA1 on TFBGA361?

[MWalk.3]

I have a design based on the STM32MP157C (technically the Octavo SiP) which simulatenously uses PA0, PA1, ANA0, and ANA1. While measuring analog signals on the device, I'm noticing that the CPU is biasing the ANA0 and ANA1 signals -- based on a measurement across a filter resistor which has a higher voltage on the CPU side than on the measurement side.

CubeMX did not generate any special pin control definitions for my use of ANA0 and ANA1; but I'm suspcious that there's either a pull up I need to disable, or the ANAx_SEL bits in SYSCFG_PMCR are not being set correctly.

What pin control settings, or ADC configuration settings, should be present in the device tree for best performance of the ANA0 and ANA1 pins?

[PatrickF · Accepted solution]

Hi @MWalk.3​ ,

there is no settings required for ANA0 and ANA1.

ANA0 and ANA1 are directly connected to the ADC (unlike other ADC inputs which have analog switches and share digital IO pins),

ANAx_SEL should be left as default ('0').

As you seems to have current flowing out of the IC, maybe worth to confirm ANAx_SEL values (e.g. using devmem2).

devmem2 0x50000A10 w 0x00000800
devmem2 0x50020004 w

Did you check that VDDA supply is present ?

With VDDA=0V, a leakage current could be present on ANA0 and ANA1 as there is protection diodes to VDDA inside the IC.

But in that case, the current will flow to the IC, and it is not what you see.

Regards.

[MWalk.3]

Patrick;

Thanks for the response; and for including the register write to enable the clock to the peripheral! I would have stared at the 0 value in the register for a while wondering why my RGMII setting was not also getting applied correctly. And you were correct that ANAx_SEL were still the default values.

I think the issue is mostly on my board; I did see that VDDA was getting pulled to 3.3V when it should have been 2.9V, but that's almost certainly something I'm doing wrong with the PMIC or that I have a unintended short somewhere.

Additionally, on reflection; my current flow into the processor is on the order of 10uA; which I believe is on the order expected by the sampling circuitry. And in any case; it turns out I'm also sampling too fast according to the datasheet. I have 1.6k input impedance and am only allowed 47 with 16bit samples.

So; all my problems are self induced, but I think I now have the tools to fix them all.

~Matt

[viniciusfre]

Hello,

I have the same issue. I have not figured out the correct pin on dts code. I have found this:

&adc {
        pinctrl-names = "default";
        pinctrl-0 = <&adc1_in6_pins_a>;
        vdd-supply = <&vddref>;
        vdda-supply = <&vddref>;
        vref-supply = <&vddref>;
        status = "okay";
        adc1: adc@0 {
                st,min-sample-time-nsecs = <10000>;
                st,adc-channels = <6>;
                status = "okay";
        };
 
        adc2: adc@100 {
                status = "disable";
        };
        adc_temp: temp {
                status = "okay";
        };
};

And adc1_in6_pins_a:

adc1_in6_pins_a: adc1-in6 {
    pins {
        pinmux = <STM32_PINMUX('F', 12, ANALOG)>;
    };
};

That would be PF12, but in my board this is a output pin and also a different pin of ANA0. So does not make sense. So what should be the dts code for the ANA0?