About MWalk.3

MWalk.3 · 2023-10-09

I'm attempting to upgrade from ecosystem v2 to v4 and I've run into an issue where the USB OTG port no longer enumerates at boot time. Specifically, I no longer see any messages in dmesg regarding the dwc device, nor do I see anything in /sys/class/u...

MWalk.3 · 2021-12-16

I have a design based on the STM32MP157C (technically the Octavo SiP) which simulatenously uses PA0, PA1, ANA0, and ANA1. While measuring analog signals on the device, I'm noticing that the CPU is biasing the ANA0 and ANA1 signals -- based on a measu...

MWalk.3 · 2021-06-25

I have a bootloader that attempts to verify the integrity of an application image before it transfers execution to the application. It does this by performing a CRC (using software) on the image. However, if the internal flash is corrupted somewhere ...

MWalk.3 · 2021-05-07

Section 28.6.4 "Temperature sensor interrupt threshold register 1 (DTS_ITR1)" of RM0455 names TS1_LITTHD as the high temperature limit, when it is in fact the low temperature limit.

MWalk.3 · 2020-09-01

I'm noticing some odd behaviour in the QUADSPI peripheral on the STM32H743. When I use the automatic status polling feature in quad mode it appears that the 1st query works as configured, but subsequent queries are strangely incomplete.What I mean by...

MWalk.3 · 2023-11-03

I have resolved this issue. At the end of the day it was *something* in the defconfig not getting set correctly. My process for generating a minimal defconfig for my setup was flawed.What did work to generate a working defconfig was to only interact ...

MWalk.3 · 2021-12-28

Patrick;Thanks for the response; and for including the register write to enable the clock to the peripheral! I would have stared at the 0 value in the register for a while wondering why my RGMII setting was not also getting applied correctly. And you...

MWalk.3 · 2021-06-28

waclawek -- In my applications I wish to continue the CRC calculation regardless of ECC errors or to escape the CRC calculation so that I can return an error. Detecting that the fault is precise, happened in the flash memory space, was an ECC error, ...

MWalk.3 · 2021-06-25

I have a small update; using the CRC engine inside the flash does not result in any error being generated while it is reading over the affected region. As in, the CRC operation completes successfully (CRCEND is set and CRCRDERR is clear), no interrup...

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User Activity

STM32MP15 USB driver not loading

What is the correct Linux pin control configuration for ANA0 and ANA1 on TFBGA361?

How to perform independent CRC on internal flash in STM32H7 (avoiding flash ECC / bus fault)?

RM0455 STM32H7A/B: 28.6.4 TS1_LITTHD is incorrectly described

STM32H7 QUADSPI Status Polling in 444 Mode

Re: STM32MP15 USB driver not loading

Re: What is the correct Linux pin control configuration for ANA0 and ANA1 on TFBGA361?

Re: How to perform independent CRC on internal flash in STM32H7 (avoiding flash ECC / bus fault)?

Re: How to perform independent CRC on internal flash in STM32H7 (avoiding flash ECC / bus fault)?