Howto configure ethernet0 MAC to MAC (without PHY, STM32MP157F)

[GLaure]

Hi!

I hope there is someone with a little experience in this topic. We are trying to get eth0 without a PHY running.

HW development decided to connect an ethernet switch (LAN9668) directly to the eth0

interface. MDIO and RGMII are connected.

We are trying to describe the device-tree using the "fixed-link" property:

&ethernet0 {
	status = "okay";
	pinctrl-0 = <&ethernet0_rgmii_pins_a &ethernet0_pps_pins_a>;
	pinctrl-1 = <&ethernet0_rgmii_sleep_pins_a &ethernet0_pps_sleep_pins_a>;
	pinctrl-names = "default", "sleep";
	phy-mode = "rgmii-id";
	max-speed = <1000>;
	//phy-handle = <&phy0>;
	nvmem-cells = <&ethernet_mac_address>;
	nvmem-cell-names = "mac-address";
 
	fixed-link {
	      speed = <1000>;
	      full-duplex;
	};
};

We removed:

	mdio0 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "snps,dwmac-mdio";
		phy0: ethernet-phy@0 {
			reg = <0>;
		};
	};
};

But we are still not able to get the link up.

With "phy0" still in, we got:

[   14.242023] stm32-dwmac 5800a000.ethernet eth0: validation of rgmii-id with support 0000000,00000000,00006280 and advertisement 00002
[   14.256200] stm32-dwmac 5800a000.ethernet eth0: no phy at addr -1
[   14.267388] stm32-dwmac 5800a000.ethernet eth0: stmmac_open: Cannot attach to PHY (error: -19)

With "fixed-link" a DMA problem is shown:

root@stm32mp1-nexio:~# dmesg | grep dwmac
[    3.058021] stm32-dwmac 5800a000.ethernet: IRQ eth_lpi not found
[    3.062928] stm32-dwmac 5800a000.ethernet: no reset control found
[    3.069358] stm32-dwmac 5800a000.ethernet: User ID: 0x40, Synopsys ID: 0x42
[    3.075900] stm32-dwmac 5800a000.ethernet:   DWMAC4/5
[    3.080703] stm32-dwmac 5800a000.ethernet: DMA HW capability register supported
[    3.087981] stm32-dwmac 5800a000.ethernet: RX Checksum Offload Engine supported
[    3.095392] stm32-dwmac 5800a000.ethernet: TX Checksum insertion supported
[    3.102286] stm32-dwmac 5800a000.ethernet: Wake-Up On Lan supported
[    3.108675] stm32-dwmac 5800a000.ethernet: TSO supported
[    3.113881] stm32-dwmac 5800a000.ethernet: Enable RX Mitigation via HW Watchdog Timer
[    3.121707] stm32-dwmac 5800a000.ethernet: device MAC address de:52:74:ca:1a:ec
[    3.128988] stm32-dwmac 5800a000.ethernet: Enabled Flow TC (entries=2)
[    3.135586] stm32-dwmac 5800a000.ethernet: TSO feature enabled
[    3.141473] stm32-dwmac 5800a000.ethernet: Using 32 bits DMA width
[   15.060089] stm32-dwmac 5800a000.ethernet: Failed to reset the dma
[   15.064879] stm32-dwmac 5800a000.ethernet eth0: stmmac_hw_setup: DMA engine initialization failed
[   15.073856] stm32-dwmac 5800a000.ethernet eth0: stmmac_open: Hw setup failed

Studying

https://wiki.st.com/stm32mpu/wiki/ETH_internal_peripheral

and

https://wiki.st.com/stm32mpu/wiki/Ethernet_device_tree_configuration

did not help.

Thanks in advance!

BTW we are still using STM32MP15-Ecosystem-v3.1.0.

Bye Gunther

[Erwan SZYMANSKI]

Hello @GLaure​ ,

Sorry for very late answer, did you manage to get this feature to work as a MAC2MAC connection ?

Kind regards,

Erwan.

[GLaure · Accepted solution]

I did. As far as I remember the problem was on the other side, the configuration of the switch.

This is the working device tree :

&pinctrl {
 
	ethernet0_rgmii_pins_x: rgmii-0 {
		pins1 {
			pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
				 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
				 <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
				 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
				 <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
				 <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
				 <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
				 <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
			bias-disable;
			drive-push-pull;
			slew-rate = <2>;
		};
		pins2 {
			pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
			bias-disable;
			drive-push-pull;
			slew-rate = <0>;
		};
		pins3 {
			pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
				 <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
				 <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
				 <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
				 <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
				 <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
			bias-disable;
		};
	};
 
	ethernet0_rgmii_sleep_pins_x: rgmii-sleep-0 {
		pins1 {
			pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
				 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
				 <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
				 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
				 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
				 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
				 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
				 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
				 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
				 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
				 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
				 <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */
				 <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
				 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
				 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
		};
	};
 
	/* ETH PPS Pin definition */
	ethernet0_pps_pins_a: eth-pps-0 {
		pins1 {
			pinmux = <STM32_PINMUX('G', 8, AF11)>; /* ETH_PPS_OUT */
			bias-disable;
			drive-push-pull;
			slew-rate = <0>;
		};
	};
 
	ethernet0_pps_sleep_pins_a: eth-pps-sleep-0 {
		pins1 {
			pinmux = <STM32_PINMUX('G', 8, ANALOG)>; /* ETH_PPS_OUT */
		};
	};
};
 
 

&ethernet0 {
	status = "okay";
	pinctrl-0 = <&ethernet0_rgmii_pins_x &ethernet0_pps_pins_a>;
	pinctrl-1 = <&ethernet0_rgmii_sleep_pins_x &ethernet0_pps_sleep_pins_a>;
	pinctrl-names = "default", "sleep";
	phy-mode = "rgmii-id";
	max-speed = <1000>;
	nvmem-cells = <&ethernet_mac_address>;
	nvmem-cell-names = "mac-address";
 
	fixed-link {
	      speed = <1000>;
	      full-duplex;
	};
 
	mdio0 {
		#address-cells = <1>;
		#size-cells = <0>;
	};
};

[Erwan SZYMANSKI]

@GLaure​ ,

Thanks a lot for your quick reply, we are glad to see that you have been able to tackle this !

Kind regards,

Erwan.