How do i boot cortex m4 in cortex A7 in Baremetal?

[Srikanth1]

Hi,

We want to boot cortex M4 from cortex A7 in baremetal in RETRAM. We have followed below steps

1.we are setting BOOT MCU bit in RCC global control register(Offset :0x10C).

2.I am restting MCURST bit in RCC global reset control set register(offset:0x404).

3.setting MCU Boot enable bit in RCC boot control register.

am i doing in correct way or not? if not can you tell the procedure of waking up the cortex M4 from cortex A7 in RETRAM.

[PatrickF]

Hi @Srikanth​ 

you should have a sequence similar to:

• RCC_MP_GCR.BOOT_MCU=0 (M4 will go in hold boot on next reset)
• RCC_MP_GRSTCSETR.MCURST = 1 (reset M4)
• wait RCC_MP_GRSTCSETR.MCURST=0 (wait reset is effective)
• enable RETRAM or other SRAMx clocks in RCC
• load FW in RETRAM and other SRAMx if needed (as all Cortex-M, there is initial SP at 0x00000000 and reset vector at 0x00000004, i.e. in RETRAM). Note that Cortex-M4 RETRAM at 0x00000000 is accessed at 0x38000000 by Cortex-A7
• RCC_MP_GCR.BOOT_MCU=1 (start M4)

Regards,

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[Srikanth1]

Thanks for reply

we will check and let you know.

[PatrickF]

Follow up seems in this post: https://community.st.com/s/question/0D53W0000216LZ7SAM/waking-up-cortex-m4-from-cortex-a70-in-stm32mp1-for-bare-metal

If related to same topic, better in future to stick to one post.

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[Srikanth1]

Hello @PatrickF​ 

Thanks for the reply.

We followed as per your suggestion.

In uboot we followed below steps.

1.rproc init

2.we copied image to RETRAM(0x38000000) manually.

3.Instead of rproc start command we written BOOT_MCU bit to set manually.

It is working fine.

In bare metal we followed step2 and 3 in above uboot sequence.

We have one quarries,

1.In rproc init command what is happening? Can you just help us in this regards?

2.how can we keep MCU in Csleep mode?

3.How can we reset the MCU?

4.How do we know whether reset is asserted or not?

Regards

Srikanth

[PatrickF]

Hi,

1. I don't know, maybe check uBoot source code
2. to keep MCU in CSleep forever, disable all interrupts in NVIC and execute WFI instruction on Cortex-M4
3. Cortex-M4 is rest using RCC_MP_GRSTCSETR.MCURST = 1
4. reading RCC_MP_GRSTCSETR.MCURST=1 mean the reset is asserted. HW automatically clear to 0 when reset is done (value at 1 could be extremely short and maybe not even visible by A7 SW).

Regards.