Ethernet on STM32MP157A with PHY AR8035 no PHY found

jhi · ‎2022-01-07

I have a problem to get the ethernet to work with the PHY AR8035 (Atheros). The board is from MYiR (MYC-YA157C-V2), but they are only providing yocto based image and I'm doing my work with buildroot. I'm using the bootlin buildroot branch: st/2021.02 https://github.com/bootlin/buildroot.git

The kernel can't find MDIO: mdio_bus stmmac-0: MDIO device at address 6 is missing.

The funny thing is, if I first boot the board from eMMC where the original image from MYiR is flashed, and afterwards, without switching power off, I start my image from the sdcard, the ethernet works. I guess this means that some register value is wrong, but I don't know where to start look. This also means that address 6 for the MDIO is also correct.

On TF-A I have CLK_ETH_DISABLED, because the 125MHz is coming from the PHY.

Below is the device tree for the kernel (CONFIG_AT803X_PHY=y is set):

&ethernet0 {
	interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
						<&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
						<&exti 70 1>;
	interrupt-names = "macirq",
				"eth_wake_irq",
				"stm32_pwr_wakeup";
 
	clock-names = "stmmaceth",
				"mac-clk-tx",
				"mac-clk-rx",
				"eth-ck",
				"ethstp";
 
	clocks = <&rcc ETHMAC>,
			<&rcc ETHTX>,
			<&rcc ETHRX>,
			<&rcc ETHCK_K>,
			<&rcc ETHSTP>;
					
	status = "okay";
	pinctrl-0 = <&eth1_pins_mx>;
	pinctrl-1 = <&eth1_sleep_pins_mx>;
	pinctrl-names = "default", "sleep";
	phy-mode = "rgmii";
	max-speed = <1000>;
	phy-handle = <&phy0>;
	nvmem-cells = <&ethernet_mac_address>;
	nvmem-cell-names = "mac-address";
 
	mdio0 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "snps,dwmac-mdio";
		phy0: ethernet-phy@6 {
			reg = <6>;
			qca,clk-out-frequency = <125000000>;
                        qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
			reset-assert-us = <1000>;
			reset-deassert-us = <2000>; 
			reset-gpios = <&gpiog 0 GPIO_ACTIVE_LOW>;
		};
	};
};

I have added the "eth-ck", because I read somewhere that it would be needed on all cases (it doesn't also work without it). Do I need to enable something else on TF-A or in u-boot?

jhi · ‎2022-01-12

So finally success!

I have changed the atheros driver to make a phy reset on link notify change (PHY_NOLINK) and do the ar8035_phy_fixup.

View solution in original post

OlivierK · ‎2022-01-11

Hi jhi (Community Member),

For the buildroot version branch you are currently using, please refer to

https://wiki.st.com/stm32mpu-ecosystem-v2/wiki/Ethernet_device_tree_configuration

then section 3.3.4 for your configuration.

Regarding the menuconfig and clock declaration I don't see anything wrong.

Could it be linked to a low power status of the PHY? since it works from a hot reset.

Regards,

Olivier

jhi · ‎2022-01-11

Well I managed to get the mdio part to work. I guess it was the reset pin, which was giving problems. Now I have the problem that the ethernet doesn't work anymore, also even after booting from the eMMC first. I just can't get to the situation where the MDIO doesn't work, but ethernet works after hot reset, even if I clean my buildroot build and remove my fix to handle reset pin. The eth0 comes up and can detect link up/down when connecting/disconnecting the cable, but no packets on RX counter. My guess would be 125MHz, but I can't measure it because the whole thing is under a metal case. Any other ideas?

Edit: Just measured: 125MHz comes when the link is up.

OlivierK · ‎2022-01-11

Some more hints:

Extract from AR8035 DS:

NOTE: CLK_25M default outputs 25MHz, can be configured to 50MHz, 62.5MHz, or 125MHz by register MMD7 8016[4:3].

->Definately check that you receive 125MHz on PG5.

Also, Atheros Green Ethos® power savings include ultra-low power in cable unplugged mode or port power down mode, and automatic optimized power saving based on cable length

-> check that you are not in this mode, or disable power saving mode.

Since ST and Bootlin company announced partnership from DV3.1 to support an official buildroot distribution this community is opened to this topic !

Bootlin support space you will find at this link :

Announcing buildroot-external-st, Buildroot support for STM32MP1 platforms - Bootlin's blog

->I may have been mislead, are you on kernel 5.4.x or 5.10.x ?

jhi · ‎2022-01-11

Yes, I get the 125MHz when the ethernet is up (when it's down it gives 25MHz).

With the fix to take care of the reset pin, the EEE mode is also switched off. Otherwise the link is switching up and down.

/* Ar803x phy SmartEEE feature cause link status generates glitch,
         * which cause ethernet link down/up issue, so disable SmartEEE
         */
        phy_write(dev, 0xd, 0x3);
        phy_write(dev, 0xe, 0x805d);
        phy_write(dev, 0xd, 0x4003);
 
        val = phy_read(dev, 0xe);
        phy_write(dev, 0xe, val & ~(1 << 8));

Here the pin configuration

ethernet0_rgmii_pins_a: rgmii-0 {
    pins1 {
	pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
	<STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
	<STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
	<STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
	<STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
	<STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
	<STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
	<STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */
	<STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
	bias-disable;
	drive-push-pull;
	slew-rate = <2>;
	};
	pins2 {
	pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
        <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
	<STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
	<STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
	<STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
	<STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
	<STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
	bias-disable;
	}
};
 ethernet0_rgmii_pins_sleep_a: rgmii-sleep-0 {
	pins1 {
		pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
			<STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
			 <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
			 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
			 <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
			 <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
			 <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
			 <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
			 <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
			 <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
		 <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
			 <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */
			 <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
			 <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
			 <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
	};
};

I'm on kernel 5.10.

VRoma.2 · ‎2022-01-11

Hi jhi (Community Member)

MYiR uses fixup code to initialize AR8035.

Here it is:

static int ar8031_phy_fixup(struct phy_device *dev)
{
	u16 val;
 
             /* To enable AR8031 output a 125MHz clk from CLK_25M */
        phy_write(dev, 0xd, 0x7);
        phy_write(dev, 0xe, 0x8016);
        phy_write(dev, 0xd, 0x4007);
 
        val = phy_read(dev, 0xe);
        val &= 0xffe3;
        val |= 0x18;
        phy_write(dev, 0xe, val);
 
        phy_write(dev, 0x1d, 0x5);
        val = phy_read(dev, 0x1e);
        val |= 0x0100;
        phy_write(dev, 0x1e, val);
	return 0;
}
 
static int ar8035_phy_fixup(struct phy_device *dev)
{
        u16 val;
 
        /* Ar803x phy SmartEEE feature cause link status generates glitch,
         * which cause ethernet link down/up issue, so disable SmartEEE
         */
        phy_write(dev, 0xd, 0x3);
        phy_write(dev, 0xe, 0x805d);
        phy_write(dev, 0xd, 0x4003);
 
        val = phy_read(dev, 0xe);
        phy_write(dev, 0xe, val & ~(1 << 8));
 
        /*
         * Enable 125MHz clock from CLK_25M on the AR8031.  This
         * is fed in to the IMX6 on the ENET_REF_CLK (V22) pad.
         * Also, introduce a tx clock delay.
         *
         * This is the same as is the AR8031 fixup.
         */
        ar8031_phy_fixup(dev);
 
        /*check phy power*/
        val = phy_read(dev, 0x0);
        if (val & BMCR_PDOWN)
                phy_write(dev, 0x0, val & ~BMCR_PDOWN);
 
        return 0;
}

This code disables SmartEEE, switch phy's PLL to 125 MHz output and enables TX delay.

Latter two is mandatory.

Which phy driver did your kernel load? Generic variant or native Atheros AR8035?

Did it post DMA reset error message?

Could you provide bootlog, please?

Regards, Vlad.

jhi · ‎2022-01-12

Yes I'm aware of this patch. I have it already implemented. Actually I applied every single change for kernel, u-boot and tf-a which MYiR made to theirs, and still the ethernet doesn't work.

The kernel loads AR8035 and I didn't get DMA error messages:

# ifconfig eth0 192.168.1.1
[   25.390211] stm32-dwmac 5800a000.ethernet eth0: PHY [stmmac-0:06] driver [Qualcomm Atheros AR8035] (irq=POLL)
[   25.407001] dwmac4: Master AXI performs any burst length
[   25.410895] stm32-dwmac 5800a000.ethernet eth0: No Safety Features support found
[   25.418598] stm32-dwmac 5800a000.ethernet eth0: IEEE 1588-2008 Advanced Timestamp supported
[   25.427263] stm32-dwmac 5800a000.ethernet eth0: registered PTP clock
[   25.433880] stm32-dwmac 5800a000.ethernet eth0: configuring for phy/rgmii link mode
# [   28.559963] stm32-dwmac 5800a000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx
[   28.567039] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready

# ifconfig
eth0      Link encap:Ethernet  HWaddr DE:12:F8:B8:BF:82
          inet addr:192.168.1.1  Bcast:192.168.1.255  Mask:255.255.255.0
          inet6 addr: fe80::dc12:f8ff:feb8:bf82/64 Scope:Link
          UP BROADCAST RUNNING MULTICAST  MTU:1500  Metric:1
          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
          TX packets:9 errors:0 dropped:0 overruns:0 carrier:0
          collisions:0 txqueuelen:1000
          RX bytes:0 (0.0 B)  TX bytes:726 (726.0 B)
          Interrupt:52 Base address:0x2000

The bootlog is included as a file.

jhi · ‎2022-01-12

So finally success!

I have changed the atheros driver to make a phy reset on link notify change (PHY_NOLINK) and do the ar8035_phy_fixup.

VRoma.2 · ‎2022-01-12

Atheros driver in case of rgmii phy mode disables both rx and tx delays.

In my case i have to change phy mode (in device three) to "rgmii-id", and add gpio-reset pin then remove myir fixup code entirely.

Congtats you got the problem fixed!

jhi · ‎2022-01-12

Any idea what could be wrong with the u-boot not finding phy-handle?

Net: FEC: can't find phy-handle