Why are the DDR_DQ signals mixed in unsorted order - STM32MP157

[DMårt]

I just saw this. It's from STM32MP157 discovery board.

Notice that DQ9 is attached to E3.

This schematic is the RAM DDR memory:

They are connected correctly. The index of DQU2 is the 10:th index of DQ, also DQ10. But the naming of the net labels seems to be wrong. This picture is the footprint of the RAM DDR memory.

But here is where things getting werid.

Noticie that E3 was DDR_DQ9, but it was actually DQ0 according to the datasheet. The same for DDR_DQ5, it was DQ10.

Here is the microprocessor STM32MP157. Notice that they are not correctly indexed. My question is: Why? Why will this work according to the schematic designers?

This schematic is the symbol of the STM32MP157 processor.

[Tesla DeLorean]

Probably to simplify escape / routing.

To get the same data in and out they just need to be consistent, D0..D7 in one group, and D8..D15 in the other

It's not like a ROM/EPROM written by an external programmer, provided the RAM access is internally consistent the fact you rearrange the bit designations doesn't matter.

[DMårt]

Thank you for your reply.

So it dosen't matter the index, how I connect the D0-D15? As long as they are connected as the same when the data is written and read?

[Peter BENSCH]

Correct. As long as they remain in the same groups, it does not matter if, for example, RAM D0 bits are written to D9, because they are read from exactly the same location. The bits are then only in a different physical location within the RAM, but the CPU doesn't really care.

[PatrickF]

Hi @DMårt 

That's usual for memories. You retrieve what you have written on same byte/bits, whatever their name (obviously, you cannot mix everything as there is some protocol/timing constrains and DDR3 working on a per byte basis). 

With DDR3/DDR3L, you could swap bits within same byte and swap bytes altogether (note: if you are using only x16 on a x32 device, you must only use byte0 and byte1).

This is to allow easier routing on PCB (e.g. avoid vias, length equalization, etc...). Please have a look to AN5122. If you are not familiar with DDR routing, we provide pre-routed Altium project example on STM32MP1 product pages.

Notice that LPDDR2/3 has different constrains on data swapping (lower byte is fixed)

Regards.

[DMårt]

Thank you for your answer.

So that means if I have the data D0 to D15, I can only swap D0-D7 with each other and D8-D15 with each other?

Not mix D0-D15 compleatly with each other?

[PatrickF · Accepted solution]

Yes, you have to keep the group on a per byte basis for DQ, DQS and DQM.

I still recommend to read AN5122 and to use whenever possible an example from the ones provided in https://www.st.com/resource/en/hw_model/stm32mp15x-series-ddr-memory-routing-guidelines-examples.zip

Regards.

[DMårt]

Hi!

What do you mean with "keep the group on a per byte basis"?

I can mix the signals D0-D15 and DQS_P and DQS_N?

Yes I have read the AN5122. Good manual. Working on it. But I don't see any recommendations of which signals can be swapped.