STM32WBA52 ADC Maximum Clock Frequency & Max Sample Rate at 12-Bit Resolution

[rajdeep_01]

Hi Enthusiastic,

MCU: STM32WBA52CGU6
STM32CubeMX: 6.9.0
STM32CubeIDE: 1.12.0
Toolchain - GNU Tools for STM32: 11.3rel1
SDK - STM32CubeWBA: V1.1.1

Query related to maximum ADC-Clock-Frequency & maximum sample-per-second with 12-Bit Resolution ADC.
I have go through Datasheet, Reference-Manual & ST-Community,
As per mentioned and gathered information:
1. Not clearly Maximum value for ADC-Clock-Frequency in any source.
2. As per datasheet: DS14127 Rev 7: Page 47:
    https://www.st.com/resource/en/datasheet/stm32wba52ce.pdf
    Note: The ADC4 analog block clock frequency after the ADC4 prescaler must be between 140 kHz and 55 MHz.
3. As per datasheet: DS14127 Rev 7: Page 45: Table 14:
    https://www.st.com/resource/en/datasheet/stm32wba52ce.pdf
    Maximum sampling speed for 12-bit resolution: 2.5 Msps
4. As per Reference Manual RM0493 Rev 5: Page 636:
    https://www.st.com/resource/en/reference_manual/rm0493-multiprotocol-wireless-bluetooth-lowenergy-and-ieee802154-stm32wba5xxx-armbased-32bit-mcus-stmicroelectronics.pdf
    tCONV = tSMPL + tSAR = [1.5 |min + 12.5 |12bit] x tADC_CLK

    tCONV = tSMPL + tSAR = 42.9 ns |min + 357.1 ns |12bit = 0.400 µs |min (for fADC_CLK = 35 MHz)
5. In above equation taken, fADC_CLK = 35 MHz,
    As per Point-2 above, possible to feed maximum fADC_CLK = 55 MHz,
    As per Point-4 above, using fADC_CLK = 55 MHz, can achieve tCONV = 3.928 Msps.
6. Note that with trial of set fADC_CLK = 55 MHz, successfully get proper ADC readings.
7. When tried with 70 MHz, successfully get proper ADC readings.

Root question is that, is it fine to use fADC_CLK = 70 MHZ, because datasheet mentioned not but practically looks working fine, and what is real maximum allowable fADC_CLK and maximum SMPS?

Thanks.

[TDK]

You can overclock something if you want. It might work, it might not. It might work at ambient, but fail at higher/lower temperatures, or at lower voltages, or on Tuesdays.

If you want guaranteed behavior, respect the limitations given in the datasheet. Otherwise you assume all risk and the behavior is not guaranteed by ST.

[rajdeep_01]

Thanks @TDK  for quick reply,
Just want to know that keep limit should be at 55MHz or 35MHz,
55Mhz is as per clearly mentioned max fADC_CLK limit in datasheet,
35 MHz as per mentioned max sampling 2.5MSPS limit in datasheet.

Thanks.