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SMPS - Danger the device may be destroyed

Associate III

Hi all,

I read this advertising in the datasheet:


The SMPS needs a clock to be functional. If for any reason this clock stops, the device may

be destroyed.


Danger: Before enabling the SMPS, the SMPS clock detection must be enabled in the sub-GHz radio SUBGHZ_SMPSC0R.CLKDE.


I only found references to SUBGHZ_SMPSC0R in:

  • STM32Cube_FW_WL_V1.0.0\Middlewares\Third_Party\SubGHz_Phy\stm32_radio_driver\radio_driver.h

#define SUBGHZ_SMPSC0R 0x0916

  • STM32Cube_FW_WL_V1.0.0\Projects\NUCLEO-WL55JC\Examples\PWR\PWR_SMPS\Src\main.c

Use example

In the Datasheet:


The LDO or SMPS step-down converter operating mode can be configured by one of the


• by the MCU using the SMPSEN setting in PWR control register 5 (PWR_CR5), that

depends upon the MCU system operating mode (Run, Stop, Standby or Shutdown).

• by the sub-GHz radio using SetRegulatorMode() command and the sub-GHz radio

operating mode (Sleep, Calibrate, Standby, Standby with HSE32 or Active).

After any POR and NRST reset, the LDO mode is selected. The SMPS selection has priority

over LDO selection.


I don´t find any reference about "SetRegulatorMode()"

In the Reference Manual:


PWR control register 5 (PWR_CR5) --> Reset value: 0x0000 0000

Bit 15 SMPSEN: SMPS step-down converter enable

This bit enables the SMPS step-down converter.

0: SMPS step-down converter SMPS mode disabled (LDO mode enabled)

1: SMPS step-down converter SMPS mode enabled

Caution: Before enabling the SMPS, the SMPS clock detection must be enabled in the subGHz radio SUBGHZ_SMPSC0R.CLKDE.

Bit 14 RFEOLEN: sub-GHz radio end-of-life detector enable

0: Radio end-of-life detector disabled

1: Radio end-of-life detector enabled

Bits 13:0 Reserved, must be kept at reset value.


In the radio_driver.h code:


/*Sub-GHz radio SMPS control 0 register */

#define SUBGHZ_SMPSC0R 0x0916


/*Sub-GHz radio SMPS control 2 register */

#define SUBGHZ_SMPSC2R 0x0923


The SUBGHZ_SMPSC2R registers is used by:

static void Radio_SMPS_Set(uint8_t level)

If I use Applications\LoRaWAN\LoRaWAN_End_Node in the Nucleo-WL55JC1

Is SMPS enabled by the LoRa radio Driver?

Do I have to worry about this "device may be destroyed" warning?

Do I have to implement clock detection?

Best Regards


Associate III

Thanks for getting back to me. I know I replied on the other thread, but I'll document it here too in case others aren't reading the other thread. I'm enabling the clock protection, but I think something else is going on that's APB3/SPI bus related before it even gets to the radio section. In the debugger, the SUBGHZ SPI registers all show up as 0 and never change when writing to them, and they always read back as 0. Writing anything to SPI registers in APB3 (0x58010000 region) does nothing. So it's an issue on the APB3/PCLK3 bus, before it even gets to the radio. I'm way under the 16Mhz max SPI limit, so it shouldn't be an overclocked issue that has damaged it.