2021-09-04 12:42 PM
Hi - I'm having a real struggle with the SAI peripheral. I've tried on both H742, and WB55 module, and am running into the same problem.
I have the source set up in the clock config (Tried both PLL1 and PLL2, and using PLLSA1P on WB), and made sure I correctly configured and enabled the appropriate PLLs). Enabled the SAI peripheral, with what seemed like reasonable defaults in the SAI registers. Configured the SAI pins as AF6. (PE4, 5, 6 on H7) Anywhere you'd troubleshoot first?
Surface level problem: SAI SA_xDR reads 0. Deeper: Scope shows no signals on the SCK line. Most fundamental: The SAI_xCR1, SAIEN field shows 0, even if read immediately after setting it
Here's a selection of register readings from H742 after (attempting to) enabling SAI1:
Any ideas where to troubleshoot? The clearest way to solve this: What would block the SAI from enabling entirely? Of note, the other writes I do to the same reg (eg MODE above) work. Thank you.
Solved! Go to Solution.
2021-09-08 07:18 AM
Hi @DOCon.1 ,
Is your code generated with STM32CubeMX?
Did you tried to debug your code? For some peripherals, the enable bit shouldn't be set before completing some setup.
With debug, you can check which function call prevents SAIEN from being set.
You can also have a look to some examples provided in dedicated STM32Cube packages (depends on the exact product you selected):
-Amel
To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.
2021-09-08 07:18 AM
Hi @DOCon.1 ,
Is your code generated with STM32CubeMX?
Did you tried to debug your code? For some peripherals, the enable bit shouldn't be set before completing some setup.
With debug, you can check which function call prevents SAIEN from being set.
You can also have a look to some examples provided in dedicated STM32Cube packages (depends on the exact product you selected):
-Amel
To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.
2021-09-11 03:44 PM
No. I'm making the reg writes in Rust. It turns out, this was caused by not properly offsetting the FRL bits by 1, leading to an odd-numbered value. (I was setting the frame length directcly, when the proper code is frame length - 1, as annotated by the register description) So, error on my part. Thank you.
2021-09-12 01:01 AM
And this led to SAIEN remaining zero after being set?
JW
2021-09-14 07:39 PM
Correct.