Not getting interrupt from CPU2 to begin advertising state.

[Louis1]

It seems I am having the same problem here: https://community.st.com/s/question/0D50X0000Az4HdhSQE/cant-get-the-advertising-state?t=1613668936202. Except the solution for that question was to make sure the memory buffer was mapped properly to SRAM2 and to be sure I have the missing IPCC interrupt handlers. However, I have the memory mapped correctly to SRAM2 and I have the IPCC interrupt handlers.

So I'm wondering what I'm missing. Most of my code is very similar to the BLE_Datathroughput Nucleo example except I'm using FreeRTOS.

I was looking at Figure 65 in this application note: https://www.st.com/content/ccc/resource/technical/document/application_note/group1/43/ea/2f/dc/10/a3/46/e6/DM00598033/files/DM00598033.pdf/jcr:content/translations/en.DM00598033.pdf. And I am able to send TL_Enable() but then I never get a signal back from CPU2.

Any advice is much appreciated!

[Christophe Arnal]

Hello,

As long as you are planning to use FreeRTOS, you may refer to the Heart Rate example running on FreeRTOS.

Otherwise, as long as you do not receive the ready from the CPU2 ( and assuming you properly implemented the IPCC interrupt handler as done in the other projects ), the only reason I see is that CPU2 is not happy with some initialization parameter.

Please make sure option byte IPCCDBA is set to 0 and check the value written @0x20030000.

if the CPU2 is not happy with some initialization parameter, it will consider this as an attack attempt and will lock all activity to avoid any security leak.

The AN5289 is listing the content that you could read when such error is detected. This is listed in chapter 4.8.2 SRAM2

Regards.

[DPesk.1]

Hello,

Can you help to find the mistake. I've the same problem, but after jumping from bootloader apps to main apps.

I click "Start Debug" button in the Keil. Program is running. But CPU2 is Hardfault. In SRAM2a I see Hardfault code and another information about it (AN5289):

1) Program counter value that generate the hardfault: 0x0002607C

2) Link register...: 0x0001FE1B

3) Stack pointer....: 0x2003F1F0

But i can't find information about it anywhere.

My program start from 0x08010000 and SRAM from 0x20000004.

If Bootloader started in OTA mode - BLE is working fine.

But if Bootloader jump to the main program - BLE is not working. And if I start the debug session for main program from the Keil too. Another functions in my main program (graphics, display, interrupts...) working fine. Only CPU2 doesn't work.

All buffers for CPU2 stay in SRAM2 memory. I checked it.

Jump function in the bootloader.

static void jump_to_main_fw(void)
{
    typedef void (*fct_t)(void);
	fct_t app_reset_handler;
	
	SCB->VTOR = FLASH_ADDRESS_MAIN_PROGRAM;
	__set_MSP(*(uint32_t*)(FLASH_ADDRESS_MAIN_PROGRAM));
	app_reset_handler = (fct_t)(*(uint32_t*)(FLASH_ADDRESS_MAIN_PROGRAM + 4));
	app_reset_handler();
 
	/**
	* app_reset_handler() never returns.
	* However, if for any reason a PUSH instruction is added at the entry of  JumpFwApp(),
	* we need to make sure the POP instruction is not there before app_reset_handler() is called
	* The way to ensure this is to add a dummy code after app_reset_handler() is called
	* This prevents app_reset_handler() to be the last code in the function.
	*/
	__WFI();
}

Linker file for main program:

LR_IROM1 0x08010000 0x00000FFC  {    ; load region size_region
  ER_IROM1_LOW 0x08010000 0x00000FFC  {  ; load address = execution address
   *.o (RESET, +First)
  }
  
  
  RW_IRAM1     0x20000004 0x2FFFC  {  ; RW data
   .ANY (+RW +ZI)
  }
  RW_RAM_SHARED 0x20030000 0x2800  {  ; RW data
   *(MAPPING_TABLE)
   *(MB_MEM1)
   *(MB_MEM2)
  }
}
 
LR_IROM2 0x08010FFC 0x4 {
  ER_IROM1_MED 0x08000FFC 0x4  {  ; load address = execution address
   *.o (TAG_OTA_START)
  }
 }
 
LR_IROM3 0x08011000 0xEF000 {
  ER_IROM1_HIGH 0x08011000 0xEF000 {  ; load address = execution address	
	*(InRoot$$Sections)
	.ANY (+RO)  
	*.o (TAG_OTA_END)	
  }
}

Could you tell How can i check it?

Thanks

[Christophe Arnal]

​Hello,

Hardfault on CPU2 is hard to generate. The only reason I would see is that at some point in time, the buffers addresses  given by CPU1 are not 32bits aligned.

Could you please tell me which CPU2 version you are running ? ( I believe you are running the BLE Full stack binary but I would need the version )

Regards

[DPesk.1]

Hello,

I changed linker file (as in your exapmle Ble_hearterate_ota) and now CPU2 is working after jump. I use 1.1.10 version for FULL BLE STACK in cpu2.

Can you tell why in your program OTA_TAG_START shift in 0x40 after start of main program, but in my program with your code (from example) OTA_TAG_START shift in 0x13C...

[Christophe Arnal]

​Hello,

I believe you made a typo in the version. You may refer to 1.11.0 and not 1.1.10 but as long as you dont have the hard fault anymore, it does not matter.

I am not sure to understand your issue with OTA_TAG_START . In our exemple, this TAG shall always be at 0x140 from the base address. You may check this in the mapping file.

Here is what can be found in the mapping output from IAR when compiling BLE_HearRAte_ota

"P1":                                            0x4
  TAG_OTA_START          const    0x08007140     0x4  app_ble.o [1]
                                - 0x08007144     0x4

BLE_HearRAte_ota is linked at start address 0x08007000 so OTA_TAG_START  is at 0x08007140.

Regards.