Hi Everyone I have a some difficulties with bringing up the HD40015C40-Y display with TouchGFX or even at all:
1. I used the init code provided by adafruit, I set up my SPI with 9bit words and sent it to the display as per the datasheet for the NV3052CRGB datasheet.
2. TouchGFX is already setup and LTDC is setup to the timings described in the https://www.adafruit.com/product/5793 init code.
3. I have very strange rainbow lines behaviour
Currently I am running a 35Mhz clock. The 35Mhz clock was derived from the linux device tree overlay for the HD40015C40-Y display.
4. Things I do know: SPI transmission definitely works. There are physical signals for the LTDC pins coming from the STM chip as I checked with an oscilloscope.
Interestingly if you read the Circuit Python code from Adafruit, they only have 16Mhz frequency.
I have no idea if this is a software problem, hardware problem or a combination of both.
void Wrt_Reg_3052(uint8_t Par1,uint8_t Par2)
{
// 9 bit mode
command = 0;
command|= Par1;
parameter = 256;
parameter |= Par1;
HAL_GPIO_WritePin(CS_PIN_GPIO_Port, CS_PIN_Pin ,GPIO_PIN_RESET);
HAL_SPI_Transmit(&hspi1, (uint8_t*)&command,1, 1000);
HAL_SPI_Transmit(&hspi1, (uint8_t*)¶meter,1, 1000);
HAL_GPIO_WritePin(CS_PIN_GPIO_Port, CS_PIN_Pin, GPIO_PIN_SET);
}
uint8_t NV3051D_Init()
{
Wrt_Reg_3052(0xFF,0x30);
Wrt_Reg_3052(0xFF,0x52);
Wrt_Reg_3052(0xFF,0x01);
Wrt_Reg_3052(0xE3,0x00);
Wrt_Reg_3052(0x0A,0x11);
Wrt_Reg_3052(0x23,0xA0);//A2
Wrt_Reg_3052(0x24,0x32);
Wrt_Reg_3052(0x25,0x12);
Wrt_Reg_3052(0x26,0x2E);
Wrt_Reg_3052(0x27,0x2E);
Wrt_Reg_3052(0x29,0x02);
Wrt_Reg_3052(0x2A,0xCF);
Wrt_Reg_3052(0x32,0x34);
Wrt_Reg_3052(0x38,0x9C);
Wrt_Reg_3052(0x39,0xA7);
Wrt_Reg_3052(0x3A,0x27);
Wrt_Reg_3052(0x3B,0x94);
Wrt_Reg_3052(0x42,0x6D);
Wrt_Reg_3052(0x43,0x83);
Wrt_Reg_3052(0x81,0x00);
Wrt_Reg_3052(0x91,0x67);
Wrt_Reg_3052(0x92,0x67);
Wrt_Reg_3052(0xA0,0x52);
Wrt_Reg_3052(0xA1,0x50);
Wrt_Reg_3052(0xA4,0x9C);
Wrt_Reg_3052(0xA7,0x02);
Wrt_Reg_3052(0xA8,0x02);
Wrt_Reg_3052(0xA9,0x02);
Wrt_Reg_3052(0xAA,0xA8);
Wrt_Reg_3052(0xAB,0x28);
Wrt_Reg_3052(0xAE,0xD2);
Wrt_Reg_3052(0xAF,0x02);
Wrt_Reg_3052(0xB0,0xD2);
Wrt_Reg_3052(0xB2,0x26);
Wrt_Reg_3052(0xB3,0x26);
Wrt_Reg_3052(0xFF,0x30);
Wrt_Reg_3052(0xFF,0x52);
Wrt_Reg_3052(0xFF,0x02);
Wrt_Reg_3052(0xB1,0x0A);
Wrt_Reg_3052(0xD1,0x0E);
Wrt_Reg_3052(0xB4,0x2F);
Wrt_Reg_3052(0xD4,0x2D);
Wrt_Reg_3052(0xB2,0x0C);
Wrt_Reg_3052(0xD2,0x0C);
Wrt_Reg_3052(0xB3,0x30);
Wrt_Reg_3052(0xD3,0x2A);
Wrt_Reg_3052(0xB6,0x1E);
Wrt_Reg_3052(0xD6,0x16);
Wrt_Reg_3052(0xB7,0x3B);
Wrt_Reg_3052(0xD7,0x35);
Wrt_Reg_3052(0xC1,0x08);
Wrt_Reg_3052(0xE1,0x08);
Wrt_Reg_3052(0xB8,0x0D);
Wrt_Reg_3052(0xD8,0x0D);
Wrt_Reg_3052(0xB9,0x05);
Wrt_Reg_3052(0xD9,0x05);
Wrt_Reg_3052(0xBD,0x15);
Wrt_Reg_3052(0xDD,0x15);
Wrt_Reg_3052(0xBC,0x13);
Wrt_Reg_3052(0xDC,0x13);
Wrt_Reg_3052(0xBB,0x12);
Wrt_Reg_3052(0xDB,0x10);
Wrt_Reg_3052(0xBA,0x11);
Wrt_Reg_3052(0xDA,0x11);
Wrt_Reg_3052(0xBE,0x17);
Wrt_Reg_3052(0xDE,0x17);
Wrt_Reg_3052(0xBF,0x0F);
Wrt_Reg_3052(0xDF,0x0F);
Wrt_Reg_3052(0xC0,0x16);
Wrt_Reg_3052(0xE0,0x16);
Wrt_Reg_3052(0xB5,0x2E);
Wrt_Reg_3052(0xD5,0x3F);
Wrt_Reg_3052(0xB0,0x03);
Wrt_Reg_3052(0xD0,0x02);
Wrt_Reg_3052(0xFF,0x30);
Wrt_Reg_3052(0xFF,0x52);
Wrt_Reg_3052(0xFF,0x03);
Wrt_Reg_3052(0x08,0x09);
Wrt_Reg_3052(0x09,0x0A);
Wrt_Reg_3052(0x0A,0x0B);
Wrt_Reg_3052(0x0B,0x0C);
Wrt_Reg_3052(0x28,0x22);
Wrt_Reg_3052(0x2A,0xE9);
Wrt_Reg_3052(0x2B,0xE9);
Wrt_Reg_3052(0x34,0x51);
Wrt_Reg_3052(0x35,0x01);
Wrt_Reg_3052(0x36,0x26);
Wrt_Reg_3052(0x37,0x13);
Wrt_Reg_3052(0x40,0x07);
Wrt_Reg_3052(0x41,0x08);
Wrt_Reg_3052(0x42,0x09);
Wrt_Reg_3052(0x43,0x0A);
Wrt_Reg_3052(0x44,0x22);
Wrt_Reg_3052(0x45,0xDB);
Wrt_Reg_3052(0x46,0xdC);
Wrt_Reg_3052(0x47,0x22);
Wrt_Reg_3052(0x48,0xDD);
Wrt_Reg_3052(0x49,0xDE);
Wrt_Reg_3052(0x50,0x0B);
Wrt_Reg_3052(0x51,0x0C);
Wrt_Reg_3052(0x52,0x0D);
Wrt_Reg_3052(0x53,0x0E);
Wrt_Reg_3052(0x54,0x22);
Wrt_Reg_3052(0x55,0xDF);
Wrt_Reg_3052(0x56,0xE0);
Wrt_Reg_3052(0x57,0x22);
Wrt_Reg_3052(0x58,0xE1);
Wrt_Reg_3052(0x59,0xE2);
Wrt_Reg_3052(0x80,0x1E);
Wrt_Reg_3052(0x81,0x1E);
Wrt_Reg_3052(0x82,0x1F);
Wrt_Reg_3052(0x83,0x1F);
Wrt_Reg_3052(0x84,0x05);
Wrt_Reg_3052(0x85,0x0A);
Wrt_Reg_3052(0x86,0x0A);
Wrt_Reg_3052(0x87,0x0C);
Wrt_Reg_3052(0x88,0x0C);
Wrt_Reg_3052(0x89,0x0E);
Wrt_Reg_3052(0x8A,0x0E);
Wrt_Reg_3052(0x8B,0x10);
Wrt_Reg_3052(0x8C,0x10);
Wrt_Reg_3052(0x8D,0x00);
Wrt_Reg_3052(0x8E,0x00);
Wrt_Reg_3052(0x8F,0x1F);
Wrt_Reg_3052(0x90,0x1F);
Wrt_Reg_3052(0x91,0x1E);
Wrt_Reg_3052(0x92,0x1E);
Wrt_Reg_3052(0x93,0x02);
Wrt_Reg_3052(0x94,0x04);
Wrt_Reg_3052(0x96,0x1E);
Wrt_Reg_3052(0x97,0x1E);
Wrt_Reg_3052(0x98,0x1F);
Wrt_Reg_3052(0x99,0x1F);
Wrt_Reg_3052(0x9A,0x05);
Wrt_Reg_3052(0x9B,0x09);
Wrt_Reg_3052(0x9C,0x09);
Wrt_Reg_3052(0x9D,0x0B);
Wrt_Reg_3052(0x9E,0x0B);
Wrt_Reg_3052(0x9F,0x0D);
Wrt_Reg_3052(0xA0,0x0D);
Wrt_Reg_3052(0xA1,0x0F);
Wrt_Reg_3052(0xA2,0x0F);
Wrt_Reg_3052(0xA3,0x00);
Wrt_Reg_3052(0xA4,0x00);
Wrt_Reg_3052(0xA5,0x1F);
Wrt_Reg_3052(0xA6,0x1F);
Wrt_Reg_3052(0xA7,0x1E);
Wrt_Reg_3052(0xA8,0x1E);
Wrt_Reg_3052(0xA9,0x01);
Wrt_Reg_3052(0xAA,0x03);
Wrt_Reg_3052(0xFF,0x30);
Wrt_Reg_3052(0xFF,0x52);
Wrt_Reg_3052(0xFF,0x00);
Wrt_Reg_3052(0x36,0x0A);
Wrt_Reg_3052(0x11,0x00);
HAL_Delay(200);
Wrt_Reg_3052(0x29,0x00);
HAL_Delay(100);
for (int i = 0; i < 50; i++){
HAL_GPIO_TogglePin(GPIOD, USER_LD2_RED_Pin|USER_LD3_GREEN_Pin);
HAL_Delay(30);
}
return 1;
}
