Wrong flash latency from CubeMX with STM32F302CC?

[Moritz Diller]

Posted on May 19, 2018 at 19:51

My program crashes with the following error in TrueStudio:

''Program received signal SIGTRAP, Trace/breakpoint trap.

0xfffffffe in ?? ()''

The fault occurs in line 692 of stm32f3xx_hal_rcc.c:

__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);

If I change

HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0)

to

HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1)

everything works fine.

I use an external 12 MHz clock source and this configuration in CubeMX 4.25.1:

According to RM0365 the flash access time depends on HCLK not SYSCLK like in RM0008 (STM32F1...), but I tried two other configurations which indicate that flash latency should rather be set according to SYSCLK:

SYSCLK = 72 MHz, HCLK = 9 MHz -> program crashes

SYSCLK = 48 MHz, HCLK = 12 MHz -> works

Did I overlook something else or is this a bug in the reference manual / CubeMX?

[Tesla DeLorean]

Posted on May 20, 2018 at 23:02

Yes does seem a bit odd that the processor can't run at 18 MHz without zero wait states on the flash. Certainly would suggest that the flash or prefetch is running faster than advertised.

What's the power profile look like at 72 MHz with you sleeping a lot?

[waclawek.jan]

Posted on May 20, 2018 at 23:43

Is RCC_ClkInitStruct properly initialized (i.e. filled all its fields)?

__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);

Read out and check/post the RCC registers' content just before that line.

JW

[Moritz Diller]

Posted on May 21, 2018 at 09:36

Before __HAL_RCC_SYSCLK_CONFIG:

After __HAL_RCC_SYSCLK_CONFIG:

RCC_ClkInitStruct:

For measuring the power profile at HCLK = 72 MHz I inserted ''while(1);'' before the ''MX_''-functions which configure the

peripherals.

Standby current = 17 mA (probably consumption of external circuits)

Sleep current = 25 mA - 17 mA = 8 mA

Run current = 40 mA - 17 mA = 23 mA 

VDD is 2.85 V.

[waclawek.jan]

Posted on May 21, 2018 at 14:49

I can't see any obvious problem.

One more thing from reading the RM:

The prefetch buffer must be kept on (FLASH_ACR[4]=’1’) when using a prescaler different from 1 on the AHB clock.

Can you please read and check FLASH_ACR?

JW

[Moritz Diller]

Posted on May 21, 2018 at 15:05

Prefetch buffer is enabled, when the fault occurs:

[waclawek.jan]

Posted on May 22, 2018 at 14:23

no more ideas here, sorry

[Moritz Diller]

Posted on May 24, 2018 at 15:02

Today I reproduced the issue on the STM32F3DISCOVERY-Board. The external clock is provided by aDSC6003JI2A-0000 connected to PF0-OSC_IN. The behavior is the same as with the custom hardware.

All project files are attached.

________________ Attachments : ExtClkTest.zip : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006HxZF&d=%2Fa%2F0X0000000azy%2F7gPD8cbRb9oQ8WY_haylHQsnnKhA8i1g4nAvLi4zn58&asPdf=false

[Nawres GHARBI]

Posted on June 01, 2018 at 12:10

Hi Moritz, 

Yes you are right the Flash latency should be calculated based on SYSCLK for the F3 series. 

It will be fixed in the 4.26.1

[waclawek.jan]

Posted on June 02, 2018 at 11:43

GHARBI.Nawres

‌,

The RM clearly states that latency is based on HCLK:

Are you suggesting, that a serious error in RM (and, presumably, in other 'F3xx RMs) is to be fixed in CubeMX???

Jan Waclawek