Writing to STM32F767 battery backed SRAM, why can't I turn on PWR->CSR1 BRE

[Oliver Sedlacek]

I need to write to the 4kB battery backed SRAM to hold information across power cycles, but it's not working! To be more specific:

1. The debugger memory display shows the correct data in SRAM after a write.
2. The data is read successfully at any time other than after a power cycle e.g. after a reset.
3. The battery is keeping the RTC alive and well.
4. I've set up an MPU region to make the 4kB at 0x40024000 non-cacheable

Here's my code for writing to BB SRAM:

// Now write it to BB SRAM
        RCC->APB1ENR |= RCC_APB1ENR_PWREN;  // Enable power interface clock by setting the PWREN bit 
        PWR->CR1 |= PWR_CR1_DBP;             // Disable write protection 
        RCC->AHB1ENR |= RCC_AHB1ENR_BKPSRAMEN;  // Enable the backup SRAM clock by setting BKPSRAMEN
        __DMB(); 
        memcpy((void *)pSRAM, &pay, len + sizeof(uint16_t));
        __DMB(); 
        SCB_CleanDCache();
        reg = RCC->AHB1ENR;                 // definig reg as volatile forces a read
        RCC->AHB1ENR &= ~RCC_AHB1ENR_BKPSRAMEN;
        PWR->CR1 &= ~PWR_CR1_DBP;
        RCC->APB1ENR &= ~RCC_APB1ENR_PWREN;

As you can see, I'm throwing everything at beating the cache but still no joy.

[waclawek.jan]

Oliver,

Nice catch!

> I can't see it in the manual but you need to set PWR->CR1 DBP before you can set BRE.

It is documented, sort-of, but not where you'd expect it:

@Imen DAHMEN​ ,

Can please all relevant ('F2, 'F4, 'F7) RMs be updated so that the description of the PWR_CSR(1).BRE bit contains a text, outlining that this bit is in the backup domain and thus DBP has to be set before being able to write into it?

Thanks,

Jan

[Imen.D]

Hello @Community member​ ,

Thank you for bring this to my attention.

I will forward your feedback internally to look into.

Best Regards,

Imen

[waclawek.jan]

Thanks, Imen.

Jan