Why SDIO Clock Signal is generating higher radiated emissions?

[RDave.2]

Hello,

We are using STM32F765BI series MCU. We are using SD Card using the SDIO interface. It seems that when the SDIO module is Active (CLK signal is generated at 24MHz), higher emissions are observed in the spectrum. When we disable the SDIO module (Clock stops generating 24 MHZ) then emissions are drastically reduced.

1. The Trace impedance is 50 Ohm for Clock, command and Data.
2. Have placed RC filter near to the Clock pin of MCU.
3. Clock source for SDMMC1 block is from USB48_PLL.

Let us know how we can eliminate the higher emissions.

Regards

Rachit Dave

[AScha.3]

Hi, set all pins to SDcard to lowest possible speed. (medium or low) .

Put resistors in all lines, maybe 51 r.

Keep tracks short .​

And the drivers on the SDcard are also very fast and could need damping resistors close to card also.​

[DTomi.1]

Compare the measured results to the Table 61. on the page 153. in the datasheet (Electromagnetic Interference (EMI) section).

Emissions should be around 5 dBµV in the 0.1 to 30 MHz band.

If the results greatly differ from this, then the cause of excess EMI is in the PCB layout and/or the measurement setup.

[RDave.2]

Hello AScha.3,

We have placed termination resistors near MCU for all signals - Clock, Command and Data pins according to calculations and also rectified the values as per the impedance calculations.

Also have tune the signals to eliminate the overshoot and undershoot at rising and falling edge.

But the results observed are with higher emissions.

Traces are short in the design.

[RDave.2]

Hello DTomi.1

OK will check the data and revert. We are currently measuring as per CISPR32 Standards.

30MHz to 1GHz.

We have checked the setup by enabling and disabling the SDIO peripheral. By disabling the SDIO peripherals emissions are drastically reduced and are under the threshold values of CISPR 32 Standard

[AScha.3]

>set all pins to SDcard to lowest possible speed. (medium or low) .

what speed setting you use ?

[S.Ma]

Could there be more emission by coupling other PCB tracks ? Are all SDCARD crossing tracks 90 degrees with others ? In the RC filtering, could the cap be close to the receiver and R close to the transmitter ?

[RDave.2]

Emissions are around 15dbuV in the 0.1 to 30 MHz band

[AScha.3]

at ?? distance ? and radiated 30..1000 M ?

if standard measurement, thats ok.

[RDave.2]

We are using RF-explorer with 15mm H probe, (Near field antenna) for inhouse testing. (in closed environment)

and also we had observed same reflections in EMI lab, with +/- some amplitude

we are using ST MCU in multiple products, and every product have same issue.

if we disable SD clock then no harmonics observed.

is there any specific layout ? guide for SD clock?