Why does MemManage Fault occur in ITCM?

Mapyam · ‎2022-08-03

Hi,

MemManage Fault occured in ITCM when I changed the system clock and DMA channel.

Does ITCM cause errors? What are the causes of errors?

Any ideas?

I changed below:

system clock: 480MHz→400MHz

DMA: DMA2_Stream1 →BDMA_channel0

Pavel A. · ‎2022-08-04

Does the program just disable access to addresses near 0 in MPU, to trap null pointers dereference?

Tesla DeLorean · ‎2022-08-04

ConfigMPU() would certainly be something to review, or enable/disable in a bisection of the offending code. Could also isolate to specific slots within the MPU

Shouldn't be cache related as this is TCM

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Mapyam · ‎2022-08-04

>ConfigMPU() would certainly be something to review,

Does this mean I need to enable access to ITCM(0x0000'0000 ~) on the MPU?

For example, can data overflow from another area (like SRAM4 area) and access the ITCM area? Similar posts on ST Community seem to indicate that "memcpy" write data to unintended areas.

<https://community.st.com/s/question/0D50X0000AvfBVKSQ2/random-hardfault-bug-with-stm32f730>