Why do I get an Error after stetting the PLL as System clock input?

[THoda.1]

This is the code:

#include <stm32f4xx.h>

void main(void)

{

//Set up PA5(LED)

RCC -> AHB1ENR |= 0x00000001; //enables clock for GPO PA

GPIOA -> MODER |= 0x00000400; //PA Pin 5 as GPO

GPIOA -> OTYPER |= 0x00000000; //PA Pin 5 as Push/Pull

GPIOA -> OSPEEDR |= 0x00000C00; //PA Pin 5 as High speed

GPIOA -> PUPDR |= 0x00000000; //PA Pin 5 as No pull-up/down

//clock at 180mhz

RCC -> PLLCFGR &= ~(1<<22); //set HSI as PLL input

RCC -> PLLCFGR |= (1<<4); //set PLLM prescaler to 16

RCC -> PLLCFGR |= ((1<<9) | (1<<11) | (1<<12) | (1<<14)); //PLL multimpiler *360

RCC -> CFGR |= ((1<<10) | (1<<12)); //AHB1 presclaer = /4

RCC -> CFGR |= (1<<12); //AHB2 prescaler = /2

RCC -> CR |= (1<<24); //enables PLL

RCC -> CFGR |= (1<<1); //sets PLL as main clock input

while(1)

{

//main loop

GPIOA -> BSRR = (1<<5);

GPIOA -> BSRR = (1<<21);

}

}

Once I start the code and it gets to RCC -> CFGR |= (1<<1); I get an error. I do not see why? Can someone please explain me? I am using the Segger IDE. All code is written in C. It should configure the Main PLL to get the freq. from the HSI and get it to 180MHz. Once the code gets to the point where it changes the system clock source from HSI to PLL _P it crashed:

Loading target script file STM32F4xx_Target.js

Preparing target for download

Executing Reset script Reset();

Reset: Halt core after reset via DEMCR.VC_CORERESET.

Reset: Reset device via AIRCR.SYSRESETREQ.

Downloading ‘blink.elf’ to J-Link

Programming 1.1 KB of addresses 08000000 — 080004c7

J-Link: Flash download: Bank 0 @ 0x08000000: 1 range affected (16384 bytes)

J-Link: Flash download: Total time needed: 0.525s (Prepare: 0.066s, Compare: 0.041s, Erase: 0.374s, Program: 0.026s, Verify: 0.008s, Restore: 0.008s)

Download successful

T-bit of XPSR is 0 but should be 1. Changed to 1.

Stopped by vector catch

Error reading from memory

[waclawek.jan · Accepted solution]

You need to increase number of waitstates for reading from FLASH, LATENCY in FLASH_ACR.

For 180MHz, you need also to switch on "overdrive", see ODEN bit of PWR_CR register.

JW

[THoda.1]

Hey,

thank you for your quick response.

It fixed the error, but

it only works when I dont check the status registers.

From datasheet:

Entering Over-drive mode:

3. Set ODEN bit of PWR_CR register to enable the Over-drive mode and wait for the

ODRDY flag to be set in the PWR_CSR register.

My Code:

PWR  -> CR    |= (1<<17);                  //enables overdrive mode

while(!(PWR->CSR&(1<<17)));                  //checks for overdrive mode enabled

If i leave out the while loop everything works, but as soon as I put it back in the code gets stuck in that loop

[THoda.1]

Hey,

thank you for your quick response.

It fixed the error, but

it only works when I dont check the status registers.

From datasheet:

Entering Over-drive mode:

3. Set ODEN bit of PWR_CR register to enable the Over-drive mode and wait for the

ODRDY flag to be set in the PWR_CSR register.

My Code:

PWR  -> CR    |= (1<<17);                 //enables overdrive mode

while(!(PWR->CSR&(1<<17)));                  //checks for overdrive mode enabled

If i leave out the while loop everything works, but as soon as I put it back in the code gets stuck in that loop

Complete new Code:

RCC  -> PLLCFGR &= ~(1<<22);                //set HSI as PLL input

RCC  -> PLLCFGR |= (1<<4);                 //set PLLM prescaler to 16

RCC  -> PLLCFGR |= ((1<<9) | (1<<11) | (1<<12) | (1<<14)); //PLL multimpiler *360

RCC  -> CR    |= (1<<24);                 //enables PLL

PWR  -> CR    |= (1<<17);                 //enables overdrive mode

while(!(PWR->CSR&(1<<17)));                  //checks for overdrive mode ready

FLASH -> ACR   |= ((1<<0) | (1<<2));            //5 wait states

RCC  -> CFGR   |= ((1<<10) | (1<<12));           //AHB1 presclaer = /4

RCC  -> CFGR   |= (1<<12);                 //AHB2 prescaler = /2

while(!(RCC->CR&(1<<25)));                  //checks for pll lock

RCC  -> CFGR   |= (1<<1);                 //sets PLL as main clock input

[turboscrew]

Bit 17 is overdrive mode switching bit. Bit 16 is overdrive mode enable. That's if your chip is F42x or 43x. F40x and F41x don't have those bits.