Which is better CEC peripheral clock selection for STM32H743, LSI or CSI, if no LSE availabe?

[Kkuhr.1]

Like the topic says, is the CEC module expecting a clock of nominally 32.0 kHz from the LSI, or nominally a 4 MHz/122 = 32.8 kHz clock from the CSI? It seems that the tolerances for the LSI and CSI can be too large for reliable CEC communications, and since the nominal difference between LSI and CSI sources is already 2.4% so I don't want to add another 2.4% of error to begin with. I understand that the LSI cannot be trimmed, but the CSI can, so should it be software trimmed to some specific value using HSE-based system clock? My board has no LSE as there is no need for RTC, so LSE cannot be used as a clock source for CEC.

[Peter BENSCH]

Welcome, @Kkuhr.1, to the community!

It probably doesn't matter if you use the CSI or the LSI. The smallest tolerance at HDMI CEC is required for the transmission of the logical 0: 1.5 ±0.2 ms, which corresponds to a tolerance of ±13.33%.

For the STM32H743 the CSI is specified in the full temperature range with -11...+7.5%, the LSI with -7...+5%, both of which are easily within the limit, especially at room temperatures at which consumer devices operated occasionally.

Good luck!

If the problem is resolved, please mark this topic as answered by selecting Select as best. This will help other users find that answer faster.

/Peter

[Kkuhr.1]

Hi Peter and thank you for trying to answer.

Unfortunately, the way you assumed the tolerance requirement is not correct.

The smallest tolerance is not determined by the shortest period, but the longest. Transmitting the START bit has a requirement of 4.5 ms +/- 0.2 ms between falling edges, which corresponds to a tolerance requirement of about 4.4%. Receiving the start pulse with the given time periods must also be accepted as valid start pulse.

If we assume that the CEC kernel is meant to be operated at 32000 Hz LSI, 4.5 ms wouls be exactly 144 kernel clock pulses, and the tolerance of 0.2 ms would be about +/- 6 integer amount of transmit clocks, that's already a tolerance requirement of +/- 4.16%.

As the CEC peripheral does not know the CEC kernel frequency it has been fed, it does not know if I use CSI which results into 32786.9 Hz, and with same amount of 144 clock pulses, I get a 4.392ms nominal start bit length, and thus it means that the CSI clock must be within 4 MHz -6.55% to +2.14%.

Same reasoning applies, if it is meant to use the CSI clock, and I use it nominally with the 2.4% slower LSI clock, the LSI clock requirement is then 32000 Hz -1.60% to +7.56%

So contrary to what you suggest, I really do think that the clock source matters, and for example if I use this MCU in an enclosed consumer product like a soundbar, it will also have some temperature rise associated with it.

That is why I would like to know, at which kernel frequency the CEC peripheral is meant to be operated, because it is not documented anywhere. I also suggest adding that to the documentation of course.

I also have to pass the official HDMI ATC testing with this, so it is rather important. I am prepared to feed externally the LSE input with correct frequency square wave generated with a timer if necessary.