What is the response for STM32H7 DFSDM in FastSinc mode?

[jpa]

The STM32H7 reference manual revision 6 gives the FastSinc response as:

However this seems to make no sense. The first part is a normal sinc^2 filter, but the second part describes an impulse + delayed impulse, which results in a quite strange frequency response.

I might expect the second part to be (1 - z^-(2*FOSR))/(1-z^-1) instead, but could there be two typos there? Then the first null in frequency response would be at Fs/(2 * FOSR), which would be quite useful.

If the response function described in manual is correct, it would be interesting to hear in what cases this FastSinc mode is useful?

[jpa]

Ok, now that I have the hardware I've tested the impulse response myself using this code:

static void cmd_dfsdm_test(BaseSequentialStream *chp, int argc, char *argv[])
{
    RCC->APB2ENR |= RCC_APB2ENR_DFSDM1EN;
 
    DFSDM1_Channel0->CHCFGR1 = DFSDM_CHCFGR1_DFSDMEN | DFSDM_CHCFGR1_DATMPX_1 | DFSDM_CHCFGR1_CHEN;
    DFSDM1_Channel0->CHCFGR2 = 0;
    DFSDM1_Filter0->FLTCR1 = DFSDM_FLTCR1_FAST | DFSDM_FLTCR1_RCONT;
    DFSDM1_Filter0->FLTCR2 = 0;
    DFSDM1_Filter0->FLTFCR = (0 << DFSDM_FLTFCR_FORD_Pos) | (2 <<  DFSDM_FLTFCR_FOSR_Pos) | (0 << DFSDM_FLTFCR_IOSR_Pos);
    DFSDM1_Filter0->FLTCR1 |= DFSDM_FLTCR1_DFEN;
    DFSDM1_Filter0->FLTCR1 |= DFSDM_FLTCR1_RSWSTART;
 
    for (int i = 0; i < 1000; i++)
    {
        DFSDM1_Channel0->CHDATINR = (i == 100) ? 1 : 0;
        if (DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_REOCF)
        {
            chprintf(chp, "%8d %8d\n", i, DFSDM1_Filter0->FLTRDATAR >> 8);
        }
    }
}

And found out the impulse response at FOSR=3 to be (0,3,0,3,0).

So the reference manual is correct.

I'd still be interested in know for what purpose this response is desirable, but at least I now know it is not suitable for my use case.