What is the internal clock CK_INT for the STM32H7 timers?

[Intector]

Hey @eBirdman 
I know this is an old question, but I got into the situation to wonder about this too. After some research through the mystical STM documentation and some educated guesses I compiled this document. It might prevent others from the pain to find information in the STM documentation.

STM32H7B0VBT6 Timer Clock Sources

Timer	APB Bus	Base Clock Source	Timer Kernel Clock	Clock Register
TIM1	APB2	rcc_pclk2	rcc_timy_ker_ck	RCC_APB2ENR
TIM8	APB2	rcc_pclk2	rcc_timy_ker_ck	RCC_APB2ENR
TIM15	APB2	rcc_pclk2	rcc_timy_ker_ck	RCC_APB2ENR
TIM16	APB2	rcc_pclk2	rcc_timy_ker_ck	RCC_APB2ENR
TIM17	APB2	rcc_pclk2	rcc_timy_ker_ck	RCC_APB2ENR
TIM2	APB1	rcc_pclk1	rcc_timx_ker_ck	RCC_APB1LENR
TIM3	APB1	rcc_pclk1	rcc_timx_ker_ck	RCC_APB1LENR
TIM4	APB1	rcc_pclk1	rcc_timx_ker_ck	RCC_APB1LENR
TIM5	APB1	rcc_pclk1	rcc_timx_ker_ck	RCC_APB1LENR
TIM6	APB1	rcc_pclk1	rcc_timx_ker_ck	RCC_APB1LENR
TIM7	APB1	rcc_pclk1	rcc_timx_ker_ck	RCC_APB1LENR
TIM12	APB1	rcc_pclk1	rcc_timx_ker_ck	RCC_APB1LENR
TIM13	APB1	rcc_pclk1	rcc_timx_ker_ck	RCC_APB1LENR
TIM14	APB1	rcc_pclk1	rcc_timx_ker_ck	RCC_APB1LENR

Timer Clock Calculation

The actual timer kernel clock frequency depends on the APB prescaler and TIMPRE bit setting:

For APB1 Timers (rcc_timx_ker_ck):

• If CDPPRE1 = 0xx (no division) and TIMPRE = 0: Timer clock = rcc_hclk1
• If CDPPRE1 = 100 (÷2) and TIMPRE = 0: Timer clock = rcc_hclk1
• If CDPPRE1 = 101-111 (÷4 to ÷16) and TIMPRE = 0: Timer clock = 2 × rcc_pclk1
• If CDPPRE1 = 0xx (no division) and TIMPRE = 1: Timer clock = rcc_hclk1
• If CDPPRE1 = 100 (÷2) and TIMPRE = 1: Timer clock = rcc_hclk1
• If CDPPRE1 = 101 (÷4) and TIMPRE = 1: Timer clock = rcc_hclk1
• If CDPPRE1 = 110-111 (÷8 to ÷16) and TIMPRE = 1: Timer clock = 2 × rcc_pclk1

For APB2 Timers (rcc_timy_ker_ck):

• If CDPPRE2 = 0xx (no division) and TIMPRE = 0: Timer clock = rcc_hclk1
• If CDPPRE2 = 100 (÷2) and TIMPRE = 0: Timer clock = rcc_hclk1/2
• If CDPPRE2 = 101-111 (÷4 to ÷16) and TIMPRE = 0: Timer clock = 2 × rcc_pclk2
• If CDPPRE2 = 0xx (no division) and TIMPRE = 1: Timer clock = rcc_hclk1
• If CDPPRE2 = 100 (÷2) and TIMPRE = 1: Timer clock = rcc_hclk1/2
• If CDPPRE2 = 101 (÷4) and TIMPRE = 1: Timer clock = rcc_hclk1/4
• If CDPPRE2 = 110-111 (÷8 to ÷16) and TIMPRE = 1: Timer clock = 2 × rcc_pclk2

Notes:

• TIMPRE bit is located in RCC_CFGR register (bit 15)
• CDPPRE1 and CDPPRE2 are located in RCC_CDCFGR2 register
• All timers can be individually enabled/disabled via their respective enable bits
• The timer kernel clock is what feeds the timer prescaler and counter logic