What external caps are required for VCAP on STM32H7A3ZGT6 (w/o SMPS)

[JNguyen]

Below Figure 21 implies that STM32H7A3ZGT6 (w/o SMPS) is in "LDO disable" configuration. That's means I need only two 0.1uF caps for VCAP1/2, is that correct?

 

[TDK]

> STM32H7A3ZGT6 (w/o SMPS) is in "LDO disable" configuration.

LDO can either be enabled or disabled. If if is disabled, yes you only need 0.1uF caps, but you also need to supply VCORE directly which is atypical. How are you supplying VCORE?

[JNguyen]

providing 3.3V to VCAP. It seems that Figure 21 implies STM32H7A3ZGT6 (w/o SMPS) always in "LDO disable" configuration since there is no VDDLDO pin. So I want to double check.

This is configuration I plan to use: providing 3.3V to VCAP, and only 2 0.1uF caps. However, you are saying that LDO could be turned on, but it couldn't work since there are no 2.2uF caps. correct?

[TDK]

> providing 3.3V to VCAP

This is well outside the acceptable voltage range for VCAP and will not result in a functioning chip.

> It seems that Figure 21 implies STM32H7A3ZGT6 (w/o SMPS) always in "LDO disable" configuration

The figure does not imply this. VDDLDO is connected to VDD internally when the pin is missing, although the datasheet is missing this information. It's on other H7 datasheets.

https://www.st.com/resource/en/datasheet/stm32h743bi.pdf

[JNguyen]

Thanks. That clarifies a lot. In my application, there is no other voltage available beside 3.3V. So it has to be "LDO enable" configuration. So two 2.2uF are required. 0.1uF are not required. Correct?

How do I configure it as "LDO enable" per Table 33? I don't see a way in CubeMX. Or PWR control register 3 (PWR_CR3) has to be manually programmed in user code?