What does data transmission with and without parity bit look like in UART?

[MMust.5]

For example, I use 8 bit data transfer type.

There are 3 types for the parity bit in total

No parity

Even parity

Odd parity

----------------------

Even parity

I'll make an assumption that Even parity looks like this:

10011100

The first 1 from the left is the parity bit.

If the parity bit is enabled in the settings, but it does not need to be set, because the number of transmitted bits is even, should it look like this?

00111100

----------------------

Odd parity

For Odd parity looks like this?

10001100

The first 1 from the left is the parity bit.

If the parity bit is enabled in the settings, but it does not need to be set, because the number of transmitted bits is odd, should it look like this?

00011100

---------------------

No parity

If No parity is enabled in the settings, is the parity bit excluded from data transmission?

At first 8 bits were transmitted, but when I turn off the parity bit, will 7 bits be transmitted?

Or will 8 bits be transmitted, but instead of a parity bit there will be zero?

If so, is one bit wasted in data transfer that is not used?

[MMust.5]

I didn't understand. How will it be correct in ST?

Should the parity bit come after the transmitted data or is the parity bit inserted instead of the transmitted data bit?

This is right? 8E2==sBBBBBBBBPSS

[Paul1]

Sorry, but ST seems to describe UART Data/Parity different from every other MCU I've ever worked with.

Life is fun.

I'd call your Diagram 8 Data + Parity, So 8E1 or 8O1.

ST would call it 9 bits with last bit as Parity (Still 8E1 in the notation I've been exposed to, since is effectively 8 data + Parity, as parity bit isn't useable to transfer data information, Parity is part of error detection not data).

Paul

[Paul1]

This goes back to being old enough (or read enough) to know how these things were first implemented, which was shift registers and gates/flipflops/counters. The bits were shifted out and the parity was calculated using a toggle flipflop for each bit shifted out, thus the parity was only available after all data shifted out, and was appended at end. Now we sometimes calculate the parity immediately in Hardware before shifting, or even in software.

Have a look at how CRC's are calculated using shift registers with feedback, that's way more fun! It was designed so when done to itself (same CRC formula on data stream with CRC appended) the result is zero, which uses way less circuits to check for than trying to compare equals of many bits.

See Figure2 and Figure3 in: Understanding and Using Cyclic Redundancy Checks with Maxim 1-Wire and iButton Products (maximintegrated.com)

Paul

[MMust.5]

And without the parity bit in ST it will be called 8N1? 

START BIT (LOW)

BIT 0

BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

BIT 7

STOP BIT (HIGH)

[Paul1]

Correct, 8N1

You sometimes see such notation on terminal programs (I've never seen 9E1 on a terminal program)

FYI: Lately I like Coolterm, as well as TeraTerm and IONinja. IONinja is especially useful for monitoring data when a different bit of software is doing the communications.