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Accepted Solutions
Hi Karl,
I do not know the size of the data I am receiving. It depends on the frame I am sending before, and the response type of my slave (OK/Error). That is why I am using RTOR to detect end of frame, as adviced in ST32F7xx's reference manual:
This is done in my startRxDma() function. The only difference between now and my first post is that I moved its call in UART's transfer complete callback, and added check of HAL's return state:
uint8_t startRxDma(void)
{
// set timeout on idle
MODIFY_REG(huart2.Instance->RTOR, USART_RTOR_RTO, MODBUS_TIMEOUT_IN_BITS);
// enable timeout IT
SET_BIT(huart2.Instance->CR2, USART_CR2_RTOEN);
if(HAL_OK != HAL_UART_Receive_DMA(&huart2, RS485Master.RX, UART_RX_BUF_SIZE))
{
return 0;
}
else
{
return 1;
}
}
Now called by this function:
void CallbackEndTXModbus(TYPE_MODBUS *handle)
{
handle->Config.EmissionTrameEnCours = 0; //Flag pour indiquer qu'une émission est en cours
// start Rx DMA now, otherwise we may miss slave's response
if(1 == startRxDma())
{
handle->TimerTimeout = 0;
handle->ModbusCoreState = MODBUS_STATE_CORE_MASTER_FRAME_WAIT_REPLY;
}
//Statistiques
//------------
if(handle->NbTramesTx < UINT32_MAX)
{
handle->NbTramesTx++;
}
}
Called by
void InterruptionTxModbus(void)
{
SetPinMode(&RS485Master, RS485_LISTEN_MODE);
CallbackEndTXModbus(&RS485Master);
//Vu que l'on vient d'envoyer un octet, le bus n'est pas libre
RS485Master.Config.BusLibre = 0;
RS485Master.TimerBusLibre = 0;
}
Called by
void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
{
if(huart->Instance == USART2)
{
InterruptionTxModbus();
}
}
If startRxDma fails to start DMA transfer, an attempt will be done in my modbus' state machine at each call until it succeeds :
case MODBUS_STATE_CORE_MASTER_FRAME_SEND:
if(DataRS485->Config.EmissionTrameEnCours == 0)
{
// lancement de l'ecoute pour la reception si pas encore fait
if(1 == startRxDma())
{
DataRS485->TimerTimeout = 0;
DataRS485->ModbusCoreState = MODBUS_STATE_CORE_MASTER_FRAME_WAIT_REPLY;
}
// else we will try DMA reception again at next call
}
break;
Modbus is a master/slave protocol, where slaves can "speak" only when master is sending them a question, so I am expecting only a packet from my slave (no continuous streaming). Moreover, reception and transmission cannot be done simultaneously, as my hardware is half duplex, ie transmission and reception are done on the same line. So I enable reception only after the end of transmission of a packet.
Which callback are you talking about? There are so many...
Received packets are supposed to be transfered to Rx buffer (RS485Master.RX) thanks to DMA as soon as they arrive in UART's reception register, and I do not need circular buffer mode, as I am only expecting one frame per reception, as stated in my DMA's initialisation function (please look at my first post).
UART will fire a receiver timeout interrupt when an idle state of 24 bits length (value of MODBUS_TIMEOUT_IN_BITS) is detected on the line after the reception of the last character. My HAL_UART_IRQHandler will handle it:
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
{
uint32_t isrflags = READ_REG(huart->Instance->ISR);
uint32_t cr1its = READ_REG(huart->Instance->CR1);
uint32_t cr2its = READ_REG(huart->Instance->CR2);
uint32_t cr3its = READ_REG(huart->Instance->CR3);
uint32_t errorflags;
uint32_t errorcode;
/* If no error occurs */
errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE));
if (errorflags == 0U)
{
// UART in mode Receiver on DMA : receiver timeout
if (((isrflags & USART_ISR_RTOF) != 0U)
&& ((cr2its & USART_CR2_RTOEN) != 0U))
{
// WARNING do not use HAL_UART_DMAStop(), as it stops ALL DMA streams on this UART (= Rx AND Tx)
// stop Rx DMA transfer
__HAL_DMA_DISABLE(huart->hdmarx);
// clear RTOEN bit to avoid phantom timeout its
CLEAR_BIT(huart->Instance->CR2, USART_CR2_RTOEN);
// clear RTOF flag to acknowledge receiver timeout it
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
// DMA IT will fire when transfer is complete
}
else if (((isrflags & USART_ISR_RXNE) != 0U)
&& ((cr1its & USART_CR1_RXNEIE) != 0U))
{
/* UART in mode Receiver on IT ---------------------------------------------------*/
if (huart->RxISR != NULL)
{
huart->RxISR(huart);
}
return;
}
}
....
As explained in STM32F7's reference manual, DMA transfer may continue after a software disabling of the stream. The software shall wait that DMA's transfer complete interrupt fires before reading data, to ensure that all of them have been successfully transfered (sorry, I did not tell that in my first post). Here is my DMA transfer complete handler:
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
{
uint32_t tmpisr;
__IO uint32_t count = 0;
uint32_t timeout = SystemCoreClock / 9600;
/* calculate DMA base and stream number */
DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress;
tmpisr = regs->ISR;
/* Transfer Error Interrupt management ***************************************/
if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET)
{
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
{
/* Disable the transfer error interrupt */
hdma->Instance->CR &= ~(DMA_IT_TE);
/* Clear the transfer error flag */
regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex;
/* Update error code */
hdma->ErrorCode |= HAL_DMA_ERROR_TE;
}
}
/* FIFO Error Interrupt management ******************************************/
if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET)
{
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET)
{
/* Clear the FIFO error flag */
regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex;
/* Update error code */
hdma->ErrorCode |= HAL_DMA_ERROR_FE;
}
}
/* Direct Mode Error Interrupt management ***********************************/
if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET)
{
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET)
{
/* Clear the direct mode error flag */
regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
/* Update error code */
hdma->ErrorCode |= HAL_DMA_ERROR_DME;
}
}
/* Half Transfer Complete Interrupt management ******************************/
if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET)
{
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
{
/* Clear the half transfer complete flag */
regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex;
/* Multi_Buffering mode enabled */
if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
{
/* Current memory buffer used is Memory 0 */
if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)
{
if(hdma->XferHalfCpltCallback != NULL)
{
/* Half transfer callback */
hdma->XferHalfCpltCallback(hdma);
}
}
/* Current memory buffer used is Memory 1 */
else
{
if(hdma->XferM1HalfCpltCallback != NULL)
{
/* Half transfer callback */
hdma->XferM1HalfCpltCallback(hdma);
}
}
}
else
{
/* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)
{
/* Disable the half transfer interrupt */
hdma->Instance->CR &= ~(DMA_IT_HT);
}
if(hdma->XferHalfCpltCallback != NULL)
{
/* Half transfer callback */
hdma->XferHalfCpltCallback(hdma);
}
}
}
}
/* Transfer Complete Interrupt management ***********************************/
if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET)
{
if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
{
/* Clear the transfer complete flag */
regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex;
if(HAL_DMA_STATE_ABORT == hdma->State)
{
/* Disable all the transfer interrupts */
hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME);
hdma->Instance->FCR &= ~(DMA_IT_FE);
if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
{
hdma->Instance->CR &= ~(DMA_IT_HT);
}
/* Clear all interrupt flags at correct offset within the register */
regs->IFCR = 0x3FU << hdma->StreamIndex;
/* Process Unlocked */
__HAL_UNLOCK(hdma);
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
if(hdma->XferAbortCallback != NULL)
{
hdma->XferAbortCallback(hdma);
}
return;
}
if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET)
{
/* Current memory buffer used is Memory 0 */
if((hdma->Instance->CR & DMA_SxCR_CT) == RESET)
{
if(hdma->XferM1CpltCallback != NULL)
{
/* Transfer complete Callback for memory1 */
hdma->XferM1CpltCallback(hdma);
}
}
/* Current memory buffer used is Memory 1 */
else
{
if(hdma->XferCpltCallback != NULL)
{
/* Transfer complete Callback for memory0 */
hdma->XferCpltCallback(hdma);
}
}
}
/* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
else
{
if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET)
{
/* Disable the transfer complete interrupt */
hdma->Instance->CR &= ~(DMA_IT_TC);
/* Process Unlocked */
__HAL_UNLOCK(hdma);
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
}
if(&hdma_usart2_rx == hdma)
{
// for UART Rx DMA: warn higher level that a frame has been received
if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
{
// error during reception -> ignore current frame
ignoreNextReceivedFrame = 1;
}
else if(0 == ignoreNextReceivedFrame)
{
dmaTransferComplete = 1;
}
else
{
ignoreNextReceivedFrame = 0;
}
}
if(hdma->XferCpltCallback != NULL)
{
/* Transfer complete callback */
hdma->XferCpltCallback(hdma);
}
}
}
}
/* manage error case */
if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
{
if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET)
{
hdma->State = HAL_DMA_STATE_ABORT;
/* Disable the stream */
__HAL_DMA_DISABLE(hdma);
do
{
if (++count > timeout)
{
break;
}
}
while((hdma->Instance->CR & DMA_SxCR_EN) != RESET);
/* Process Unlocked */
__HAL_UNLOCK(hdma);
/* Change the DMA state */
hdma->State = HAL_DMA_STATE_READY;
}
if(hdma->XferErrorCallback != NULL)
{
/* Transfer error callback */
hdma->XferErrorCallback(hdma);
}
}
}
dmaTransferComplete and ignoreNextReceivedFrame are declared as volatile.
My DMA transfer complete callback:
static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
{
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
/* DMA Normal mode */
if (hdma->Init.Mode != DMA_CIRCULAR)
{
huart->RxXferCount = 0U;
/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
/* Disable the DMA transfer for the receiver request by resetting the DMAR bit
in the UART CR3 register */
CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
}
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Rx complete callback*/
huart->RxCpltCallback(huart);
#else
/*Call legacy weak Rx complete callback*/
HAL_UART_RxCpltCallback(huart);
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
With
void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
{
// reception on DMA
if((huart->Instance == USART2) && (1 == dmaTransferComplete))
{
// also disable DMA error flags
huart->hdmarx->Instance->CR &= ~( DMA_IT_TE | DMA_IT_DME);
huart->hdmarx->Instance->FCR &= ~(DMA_IT_FE);
frameReceived = 1;
// get nr of bytes got during this transfer
remainingBytesToTransfer = __HAL_DMA_GET_COUNTER(huart->hdmarx);
dmaTransferComplete = 0;
}
}
frameReceived is declared as volatile too.
My modbus state machine is watching frameReceived:
case MODBUS_STATE_CORE_MASTER_FRAME_WAIT_REPLY:
//On regarde si il faut décoder la trame
//**************************************
// DMA reception + timeout on idle
if(1 == frameReceived)
{
frameReceived = 0;
DataRS485->ModbusCoreState = MODBUS_STATE_CORE_MASTER_FRAME_DECODING_REPLY;
}
//si pas de reponse
if(DataRS485->TimerTimeout >= MODBUS_WRITE_RX_TIMEOUT)
{
if(0 == DataRS485->MaxTimeOutAllowed) // Ne pas mettre de Breakpoint ici pour éviter une Ré-Initialisation intempestive des Variables !
{
HandleModbusMasterTimeOut(DataRS485);
// stop ongoing DMA transfer !!!
stopRxDma();
DataRS485->ModbusCoreState = MODBUS_STATE_CORE_MASTER_FRAME_SWAP_WRITE_READ;
} else { DataRS485->MaxTimeOutAllowed--; } // Permet d'accepter des Délais de réponses plus long si nécessaire (certaines fonctions spéciales)
if(DataRS485->TimerDataAvailable == 0)
{
DataRS485->TimerDataAvailable = 2; //Relance la tempo pour pouvoir prendre en compte les datas recus
}
DataRS485->TimerTimeout = 0;
}
break;
... then in state MODBUS_STATE_CORE_MASTER_FRAME_DECODING_REPLY, a frame check will be done (last 2 bytes of a modbus frame are a CRC16 checksum):
case MODBUS_STATE_CORE_MASTER_FRAME_DECODING_REPLY:
//Statistiques
if(DataRS485->NbTrameRx < _U_LONG_MAX)
{
DataRS485->NbTrameRx++; //Stats
}
if(CheckGlobalFrameIsOk(DataRS485) == CHECK_TRAME_OK)
{
DecodageModbusMaster(DataRS485);
memset(DataRS485->RX, 0, SIZE_RX_RS485);
}
else
{
HandleModbusMasterTimeOut(DataRS485); // Simule un TimeOut pour Clôturer la requête ...
}
DataRS485->Config.DebutTrame = 0;
DataRS485->IndiceRx = 0;
DataRS485->ModbusCoreState = MODBUS_STATE_CORE_MASTER_FRAME_SWAP_WRITE_READ;
break;
With
MODBUS_CHECK_TRAME CheckGlobalFrameIsOk(TYPE_MODBUS *DataRS485)
{
uint16_t RX_CRC;
#ifndef RECEIVE_IT
// dans le cas d'une reception par DMA, la taille recue est deduite du nb d'octets restants a transmettre
DataRS485->IndiceRx = UART_RX_BUF_SIZE - remainingBytesToTransfer;
remainingBytesToTransfer = 0;
#endif
if(DataRS485->IndiceRx > 3)
{
//Calcul du CRC
RX_CRC = CRC16((unsigned char *)DataRS485->RX, (DataRS485->IndiceRx) - 2,0xFFFF);
//Si le CRC est correct
if ( ((unsigned char) (RX_CRC) == DataRS485->RX[(DataRS485->IndiceRx) - 2]) && ((unsigned char) (RX_CRC >> 8) == DataRS485->RX[(DataRS485->IndiceRx) - 1]))
{
//Statistique
if(DataRS485->NbTrameRxCrcOk < _U_LONG_MAX)
{
(DataRS485->NbTrameRxCrcOk)++;
}
if ( (DataRS485->RX[0] == pCurModBus->Address) || (DataRS485->RX[0] == MODBUS_ADR_BROADCAST) )
{
//Statistique
if(DataRS485->NbTrameRxCrcOkAdrOk < _U_LONG_MAX)
{
(DataRS485->NbTrameRxCrcOkAdrOk)++;
}
if(DataRS485->CurrentCptReceptionOKPerSecond < _U_INT_MAX)
{
DataRS485->CurrentCptReceptionOKPerSecond++;
}
DataRS485->TimerTimeout = 0;
return CHECK_TRAME_OK;
}
return CHECK_TRAME_BAD_ADRESS;
}
return CHECK_TRAME_BAD_CRC;
}
return CHECK_TRAME_TOO_SHORT;
}
remainingBytesToTransfer is volatile too.
But at reception of 3rd frame, the value stored in remainingBytesToTransfer is not the same as the one in DMA's NDTR register, although the frame in Rx buffer is correct... :thinking_face: I wonder how this can happen...
