Posted on January 22, 2012 at 23:42Hi Franck,
We confirm your findings and it is a limitation that concerns only our DMA2, and here is the detailed description :
DMA2 controller could corrupt data when managing AHB and APB2 peripherals in a concurrent way :
Description : This case is somehow critical for peripherals embedding FIFO and generates data corruption. For memories, the impact is a multiple access but the data is not corrupted. AHB Peripherals embedding FIFO are DCMI, CRYPT, HASH. on STM32F2/40xx without CRYPTO only the DCMI is impacted.
Implications: The data transferred by the DMA to the AHB peripherals could be corrupted in case
of a FIFO target or multiply accesses in case of memories access.
Workarounds : Avoid concurrent AHB and APB2 transfer using DMA2. One of the following approach could be used to solve the issue:
If DMA2 is used to manage AHB peripheral (DCMI, CRYPT, HASH), we can use the Cortex-M CPU to manage APB2 peripherals.
If DMA2 is used to manage APB2 peripheral, we can use the CPU to manage AHB peripheral (DCMI, CRYPT, HASH).
Obviously, we will update our errata on web soon .
Thank you again for your findings .
Cheers,
STOne-32 { STM32 moderator }
PS:
You have a really Nice blog.
