This is a fairly old topic, but I figured I'd chime in for future answer seekers as I have a similar goal as the original poster.
What didn't seem to be understood by some of the answering parties was that the OP wanted both devices to be mapped into independent "slots" in the memory map without needing to intervene with the controller in any way. They wanted the flash to reside at one base address and the PSRAM to reside at a different base address such that no reconfiguration would be needed to have their application code be able to access either simply by a memory access to the appropriate region.
I can now see that this is simply not going to be possible as there is only one logical chip select for each OCTOSPI/XSPI peripheral. Even of the second schematic method of using two pins for the chip select and "masking" one or the other by reconfiguring the GPIO as either pull-up or as the appropriate Alternate Function would require the application code or a driver to intervene and switch chip selects, which rules out being able to use DMAs efficiently if at all. Furthermore, both the flash and the PSRAM would reside at the same physical base address. Adding an external MUX doesn't help the situation although it would prevent one from accidentally enabling both devices, which could result in bus contention. It would have been nice if the split bus style's memory select control bit could also be routed to an external IO pin to control the mux but that still would not allow the mapping of each device into different base address slots.
My situation is a bit different as commented on in a different post. I'd like the PSRAM to be accessed as memory mapped and the flash to be accessed as a block device, mass storage style. I don't need to worry about base address conflicts, but I will need to ensure DMA is not accessing the PSRAM before I perform a block transfer to/from flash, and I'll also need to default the interface to memory mapped mode and PSRAM chip select "live" and reconfigure both the mode and the chip select(or memory select bit if I split the bus) any time I want to access flash storage.
The best answer from a software architecture and a performance standpoint is to use a device with two OSPI/XSPI peripherals, but I'm trying to fit this onto a small processor module board with a 100-Pin QFP as the max package size. I'll probably stick with the G4 series processor and virtualize the RAM accesses as I'm using the external storage to implement a virtual machine running a new language interpreter.
This post is too long, but hopefully will help clarify for future readers.
Cheers.
