I'm using an STM32G4 series microcontroller with a Type 3 DMA. It's going to be set up as a SPI slave. It will produce data of x bytes at a rate of 10 kHz and a SPI master will want to read this data at 1 kHz asynchronously. The SPI master will only get 1 set of x bytes at 1 kHz but it should be the latest data. I'm thinking about a somewhat convoluted way to make this work, but I'm wondering if there is another standard way do deal with this problem with the given peripherals.
1. The 10 kHz loop writes its x bytes to a ping pong buffer. It then writes the pointer to the address to the most recent data into a buffer in regular memory of type DMA_Channel_Typedef. Other configuration in this memory will be set up to transfer a SPI TX transfer of x bytes and has CEN set to 0.
2. When the master drives CS low then this triggers a DMAMUX Request generator 0 which will copy the DMA_Channel_Typedef memory from step one into the DMA Channel registers for a SPI TX transfer.
3. When the DMAMUX Request generator 0 completes it will trigger another DMAMUX Request generator 1 which will copy the DMA->CCR register from another fixed memory location that has CEN enabled.
4. The SPI master will need to have waited some amount of time (100 ns or so) after CS low before it clocks out data, but it will get the most recent data when CS was set low.
I haven't tried this yet. I'm assuming it's possible. Any reasons this wouldn't work or other suggestions for this problem that don't use as many DMA Channels?
