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USART not working when using HSI in STM32F769-Discovery

RCres.1
Associate III

‎2020-05-06 04:52 AM

Hi,

I am new on STM32 and I started a product prototype using STM32F769-Discovery. I developed all software using default clock configuration, which uses HSE.

Now I want to change to HSI, but USART is not working ( Not true, only works when board resets after downloading the program. When I disconnect USB cable and reconnect it, USART does not work anymore).

Below can find default config and my HSI config:

Default config (Using HSE):

/******************************************************************************
*     The system Clock is configured as follow :
*     System Clock source            = PLL (HSE)
*     SYSCLK(Hz)                     = 216000000
*     HCLK(Hz)                       = 216000000
*     AHB Prescaler                  = 1
*     APB1 Prescaler                 = 4
*     APB2 Prescaler                 = 2
*     HSE Frequency(Hz)              = 25000000
*     PLL_M                          = 25
*     PLL_N                          = 432
*     PLL_P                          = 2
*     PLL_Q                          = 9
*     PLL_R                          = 7
*     VDD(V)                         = 3.3
*     Main regulator output voltage  = Scale1 mode
*     Flash Latency(WS)              = 7
*******************************************************************************/
 
static void SystemClock_Config( void )
{
  RCC_ClkInitTypeDef        RCC_ClkInitStruct;
  RCC_OscInitTypeDef        RCC_OscInitStruct;
  RCC_PeriphCLKInitTypeDef  PeriphClkInitStruct;
 
  /* Enable Power Control clock */
  __HAL_RCC_PWR_CLK_ENABLE();
 
  /* The voltage scaling allows optimizing the power consumption when the device is
     clocked below the maximum system frequency, to update the voltage scaling value
     regarding system frequency refer to product datasheet.  */
  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
 
  /* Enable HSE Oscillator and activate PLL with HSE as source */
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
  RCC_OscInitStruct.HSEState       = RCC_HSE_ON;
  RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_ON;
  RCC_OscInitStruct.PLL.PLLSource  = RCC_PLLSOURCE_HSE;
  RCC_OscInitStruct.PLL.PLLM       = 25;
  RCC_OscInitStruct.PLL.PLLN       = 432;
  RCC_OscInitStruct.PLL.PLLP       = RCC_PLLP_DIV2;
  RCC_OscInitStruct.PLL.PLLQ       = 9;
  RCC_OscInitStruct.PLL.PLLR       = 7;
 
  HAL_RCC_OscConfig(&RCC_OscInitStruct);
 
  /* Activate the Over-Drive mode */
  HAL_PWREx_EnableOverDrive();
 
  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
     clocks dividers */
  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK;
  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7);
 
  /* LCD clock configuration */
  memset( &PeriphClkInitStruct, 0, sizeof( PeriphClkInitStruct ));
  HAL_RCCEx_GetPeriphCLKConfig( &PeriphClkInitStruct );
  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LTDC;
 
#if EW_USE_DOUBLE_BUFFER == 1
 
  /* PLLSAI_VCO Input = HSE_VALUE/PLL_M = 1 MHz */
  /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN = 364 MHz */
  /* PLLLCDCLK = PLLSAI_VCO Output/PLLSAIR = 364 MHz / 7 = 52.0 MHz */
  /* LTDC clock frequency = PLLLCDCLK / LTDC_PLLSAI_DIVR_2 = 52.0 / 2 = 26,0 MHz */
  /* These reduced LTDC clock frequency is neccessary to avoid display artefacts
     that occur on higher LTDC clock frequencies, if there is heavy memory access
     by application during display update */
  PeriphClkInitStruct.PLLSAI.PLLSAIN = 364;
  PeriphClkInitStruct.PLLSAI.PLLSAIR = 7;
 
#else
 
  /* PLLSAI_VCO Input = HSE_VALUE/PLL_M = 1 MHz */
  /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN = 417 MHz */
  /* PLLLCDCLK = PLLSAI_VCO Output/PLLSAIR = 417 MHz / 5 = 83.4 MHz */
  /* LTDC clock frequency = PLLLCDCLK / LTDC_PLLSAI_DIVR_2 = 83.4 / 2 = 41.7 MHz */
  PeriphClkInitStruct.PLLSAI.PLLSAIN = 417;
  PeriphClkInitStruct.PLLSAI.PLLSAIR = 5;
 
#endif
 
  PeriphClkInitStruct.PLLSAIDivR     = RCC_PLLSAIDIVR_2;
  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
}

My config, not working (Using HSI):

/******************************************************************************
*     The system Clock is configured as follow :
*     System Clock source            = PLL (HSI)
*     SYSCLK(Hz)                     = 216000000
*     HCLK(Hz)                       = 216000000
*     AHB Prescaler                  = 1
*     APB1 Prescaler                 = 4
*     APB2 Prescaler                 = 2
*     HSI Frequency(Hz)              = 16000000
*     PLL_M                          = 4
*     PLL_N                          = 108
*     PLL_P                          = 2
*     PLL_Q                          = 9
*     PLL_R                          = 7
*     VDD(V)                         = 3.3
*     Main regulator output voltage  = Scale1 mode
*     Flash Latency(WS)              = 7
*/
static void SystemClock_Config( void )
{
  RCC_ClkInitTypeDef        RCC_ClkInitStruct;
  RCC_OscInitTypeDef        RCC_OscInitStruct;
  RCC_PeriphCLKInitTypeDef  PeriphClkInitStruct;
 
  /* Enable Power Control clock */
  __HAL_RCC_PWR_CLK_ENABLE();
 
  /* The voltage scaling allows optimizing the power consumption when the device is
     clocked below the maximum system frequency, to update the voltage scaling value
     regarding system frequency refer to product datasheet.  */
  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
 
  /* Enable HSI Oscillator and activate PLL with HSI as source */
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
  RCC_OscInitStruct.HSIState       = RCC_HSI_ON;
  RCC_OscInitStruct.HSEState       = RCC_HSE_OFF;
  RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_ON;
  RCC_OscInitStruct.PLL.PLLSource  = RCC_PLLSOURCE_HSI;
  RCC_OscInitStruct.PLL.PLLM       = 4;
  RCC_OscInitStruct.PLL.PLLN       = 108;
  RCC_OscInitStruct.PLL.PLLP       = RCC_PLLP_DIV2;
  RCC_OscInitStruct.PLL.PLLQ       = 9;
  RCC_OscInitStruct.PLL.PLLR       = 7;
 
  HAL_RCC_OscConfig(&RCC_OscInitStruct);
 
  /* Activate the Over-Drive mode */
  HAL_PWREx_EnableOverDrive();
 
  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
     clocks dividers */
  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK;
  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7);
 
  /* LCD clock configuration */
  memset( &PeriphClkInitStruct, 0, sizeof( PeriphClkInitStruct ));
  HAL_RCCEx_GetPeriphCLKConfig( &PeriphClkInitStruct );
  PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LTDC;
 
#if EW_USE_DOUBLE_BUFFER == 1
 
  /* PLLSAI_VCO Input = HSI_VALUE/PLL_M = 4 MHz */
  /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN = 364 MHz */
  /* PLLLCDCLK = PLLSAI_VCO Output/PLLSAIR = 364 MHz / 7 = 52.0 MHz */
  /* LTDC clock frequency = PLLLCDCLK / LTDC_PLLSAI_DIVR_2 = 52.0 / 2 = 26,0 MHz */
  /* These reduced LTDC clock frequency is neccessary to avoid display artefacts
     that occur on higher LTDC clock frequencies, if there is heavy memory access
     by application during display update */
  PeriphClkInitStruct.PLLSAI.PLLSAIN = 91;
  PeriphClkInitStruct.PLLSAI.PLLSAIR = 7;
 
#else
 
  /* PLLSAI_VCO Input = HSI_VALUE/PLL_M = 4 MHz  */
  /* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN = 417 MHz */
  /* PLLLCDCLK = PLLSAI_VCO Output/PLLSAIR = 417 MHz / 5 = 83.4 MHz */
  /* LTDC clock frequency = PLLLCDCLK / LTDC_PLLSAI_DIVR_2 = 83.4 / 2 = 41.7 MHz */
  PeriphClkInitStruct.PLLSAI.PLLSAIN = 104;
  PeriphClkInitStruct.PLLSAI.PLLSAIR = 5;
 
#endif
 
  PeriphClkInitStruct.PLLSAIDivR     = RCC_PLLSAIDIVR_2;
  HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
}

Any idea of what could be happening?

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3 REPLIES 3
berendi
Principal

‎2020-05-06 05:10 AM

0693W000000WziNQAS.png

Try it with PLLM=8 and PLLN=216 instead, adjust PLLSAIN too.

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RCres.1
Associate III

‎2020-05-11 12:00 AM

Hi,

Ok, now I got:

PLLM = 8;

PLLN = 216;

PLLSAIN = 182

With these values I have fixed some issues of the GUI application running on the MCU, but USART keeps not working.

Any idea?

Kind Regards,

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RCres.1
Associate III

‎2020-05-19 03:38 AM

Hi, with current clock configuration, USART keeps not working.

Any idea?

*   System Clock Configuration
*     The system Clock is configured as follow :
*     System Clock source            = PLL (HSI)
*     SYSCLK(Hz)                     = 216000000
*     HCLK(Hz)                       = 216000000
*     AHB Prescaler                  = 1
*     APB1 Prescaler                 = 4
*     APB2 Prescaler                 = 2
*     HSI Frequency(Hz)              = 16000000
*     PLL_M                          = 8
*     PLL_N                          = 216
*     PLL_P                          = 2
*     PLL_Q                          = 9
*     PLL_R                          = 7
*     VDD(V)                         = 3.3
*     Main regulator output voltage  = Scale1 mode
*     Flash Latency(WS)              = 7

Kind Regards

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