UART4 and UART5 Receive DMA interrupt on STM32F767ZI

[MGold.1]

I am using receive DMA to mange reception of data on UART4 and UART5.

The setting of both UARTs is identical.

UAERT4_RX is using DMA1 Stream 2

UAERT5_RX is using DMA1 Stream 0

I’m using halt transmit, transmit completed callbacks and idle interrupt to manage reception on these UARTs.

The problem – instable DMA stream interrupt response.

In some case the DMA steam_x interrupt is not produced even though the UART idle interrupt is fired at the end of data reception.

The EN bit of both DMA1 streams is set.

In many cases hard reset resolves the problem.  

What might by the cause of this random behavior, and how can it be solved?

Thanks!

Best regards,

Moti Goldhirsh

[MM..1]

Reply is simple. DMA RX is perfect only for know size of data.

For example you init receive 10bytes, but realy on line is :

4 ... only idle int

7 ... only half and idle

usw

[MGold.1]

In my case the of number of data bytes in the received message is much greater than the DMA RX buffer. So I'd expect to receive a few half received and receive completed interrupts.(callbacks). But it happens that no dma stream x is produced even though an idle line interrupt is fired at the end of the message reception.