Ok, so Counters would be where you increment/decrement by 1, and then have a comparator to see if you've hit the terminal count, ie N-1, next 0 or 0, next N-1
Of these Down Counters are the simplest, as you are checking for a zero count (figure a wide OR), and then you have a static Load register, the combinational logic here being really shallow/clean. See for example how SysTick does it.
These are integer, have 50/50 duty.
The cleverer design is to use an Adder, where you have an Accumulating register, and then a constant (programmable) value you add to it at each clock cycle. Think of it as a phase angle, for 16-bit you always have 1/65536th subdivisions of the whole cycle. You take the High Order Bit(s) as your clock output, you can take multiple and put them through a SINE ROM and get sine wave via a DAC. These adders could be 16, 24 or 32-bit wide depending on how small you want the frequency divisions/granularity.
Now the high order bit might not be exactly 50/50, but it's going to be pretty close, there will be some jitter, but it will be distributed, and long term you'll get the fractional frequency you desire, and certainly adequate for serial comms, and frankly a lot of things which can tolerate jitter of edges in nano-second ranges. (would avoid radio, ethernet, etc)
Perhaps think of it like drawing a diagonal line on a computer display, the center point where it transitions to the next pixel up can change from one section to the next, the fractional error accumulates briefly, but is corrected as soon as possible, and the average comes out with the fractional division you wanted. Compare that to doing one integer division, and applying that over all the line sections, the deviation at the far end will have accumulated a lot of error that isn't addressed, ie you wanted 3.5, to do that you need 3 & 4 alternating, and not 3 & 3 or 4 & 4
