Trying to figure out I2C TIMING register

[KSchr.11]

I am trying to implement I2C communication with L432KC (bare metal coding) to interface peripherals like port expander, eeprom. But I am having a hard time figuring out the TIMING register. I have several questions:

1. tPRESC = (PRESC+1) x tI2CCLK

This is a simple one but I just wish to confirm. The I2CCLK corresponds to the standard frequency like 100khz, 400khz etc or my APB peripheral clock? I am leaning towards one of the standard frequencies since RM has mentioned peripheral clock as fPCLK in other parts.

2. There are several of these bits fields in this register, take this one for example:

Bits 15:8 SCLH[7:0]: SCL high period (master mode)

This field is used to generate the SCL high period in master mode.

tSCLH = (SCLH+1) x tPRESC

Note: SCLH is also used to generate tSU:STO and tHD:STA timing.

By "used to generate", does it imply Setup and Hold timing of STOP and START (respectively) are equal to tSCLH ?

3. How does the CubeMX and the xls file provided by ST calculate bit values by taking rise and fall times as input?

This is similar to question 2, because by taking just rise and fall times, it is calculating the setup and hold times for data, start and stop conditions.

[waclawek.jan · Accepted solution]

1. tI2CCLK is input clock of the I2C module. It's not necessarily the APB clock, although it's the default, see I2CxSEL bits in RCC_CCIPR for the 'L432.
2. Yes. Is anything wrong with that?
3. I don't know. Aren't the formulas visible?

JW

[KSchr.11]

Hey thanks for the reply. Formulas are not visible on the excel.

Anyway, I figured it all out just a couple of hours after posting by reading the I2C config tool application note. Everything was explained there. I tried deleting post but it said "administrator has disabled post and comment deletes"