Posted on November 09, 2017 at 11:38Just to give another view on this. If you use the code which was suggested above.
while (1)
{
GPIOC->ODR = GPIO_PIN_9;
GPIOC->ODR = 0;
}
It will assemble into simple STR Rx, [Ry], where Rx is the value you are writing to the ODR register which is located at address Ry. According to Technical Reference Manual Cortex M7_r0p2.pdf from ARM in section 3.3.3 Load/store timings, this instruction is single cycle. So you might expect to toggle the pin at half of the SystemClock frequency which is indeed 108 MHz. At the end of while loop there will be an unconditional branch to the beginning of while cycle. This takes 1 + P cycles, where P ranges from 1 to 3 depending on the alignment and width of the target instruction, and whether the processor manages to speculate the address early. On F4 devices you would probably see a discontinuity when this happens. On F7 you might not because of the Superscalar nature of the core. Check the following simple benchmark which was executed on F4 and F7
C code
for (n = 0; n < NUM_SAMPLES; n++)
{
acc += array1[n];
}
Assembly
??main_1:
LDR R2,[R0], #+4 // load the next value from array1
ADDS R4,R2,R4 // add it to accumulator
SUBS R1,R1,#+1 // increment loop counter
BNE.N ??main_1 // loop back
core Cycles for 500 iterations Cycles for 1iteration
M7 1024 2.048
M4 3006 6.012
As was already said, it is important that the caches are enabled to compensate for slow flash access. Either the ART caches when ITCM is used or Core caches when AXI bus is used.
Best regards,
Martin
STMicroelectronics, Microcontroller Application Support Engineer
