Timer counting too fast in input capture

John Hite · ‎2017-03-17

Posted on March 17, 2017 at 22:20

Device: STM32F437

My timer seems to count twice as fast as I think it should. My peripheral clock is running @ 42MHz and I have scaled it down to 1 KHz. I got things started and interrupts going thanks to help from JW but I noticed the count seemed wrong. The external capture event occurs every 1 second and with the clock at 1 KHz I read the count a total of 10 times . I expected the count to to go up by 1000. With TIM_Period set to 0xFFFF I read a delta of 2000 each time. A code snippet is below and the detection is set for rising edge so it seems I should capture once a second and there should be a count of 1000 in the CNT register.

Thanks,

jh

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waclawek.jan · ‎2017-03-17

Posted on March 17, 2017 at 23:37

My peripheral clock is running @ 42MHz

If it means APB clock having been scaled down from a faster AHB clock, then your timers' clock is running twice as fast as the APB clock.

Read the fine manual, RM0090, 7.2 Clocks

The timer clock frequencies are automatically set by hardware. There are two cases:

1. If the APB prescaler is 1, the timer clock frequencies are set to the same frequency as

that of the APB domain to which the timers are connected.

2. Otherwise, they are set to twice (Ã—2) the frequency of the APB domain to which the

timers are connected.

and also have a look at the clock tree schematics in the same chapter.

JW

View solution in original post

waclawek.jan · ‎2017-03-17

Posted on March 17, 2017 at 23:37

My peripheral clock is running @ 42MHz

If it means APB clock having been scaled down from a faster AHB clock, then your timers' clock is running twice as fast as the APB clock.

Read the fine manual, RM0090, 7.2 Clocks

The timer clock frequencies are automatically set by hardware. There are two cases:

1. If the APB prescaler is 1, the timer clock frequencies are set to the same frequency as

that of the APB domain to which the timers are connected.

2. Otherwise, they are set to twice (Ã—2) the frequency of the APB domain to which the

timers are connected.

and also have a look at the clock tree schematics in the same chapter.

JW

John Hite · ‎2017-03-20

Posted on March 20, 2017 at 19:29

Thanks. That seems to be the case in the long run although my processor is covered in chapter 6 with a more convoluted statement:

â€¢ If TIMPRE bit in RCC_DKCFGR register is reset:

If the APB prescaler is configured to a division factor of 1, the timer clock frequencies

(TIMxCLK) are set to PCLKx. Otherwise, the timer clock frequencies are twice the

frequency of the APB domain to which the timers are connected: TIMxCLK = 2xPCLKx.

â€¢ If TIMPRE bit in RCC_DKCFGR register is set:

If the APB prescaler is configured to a division factor of 1, 2 or 4, the timer clock

frequencies (TIMxCLK) are set to HCLK. Otherwise, the timer clock frequencies is four

times the frequency of the APB domain to which the timers are connected: TIMxCLK =

4xPCLKx.

I thank you for helping me find it as the code I was using did even address TIMPRE in the setups.

JH

waclawek.jan · ‎2017-03-20

Posted on March 20, 2017 at 20:35

Ah, I see. Sorry, seeing 'F4' I did not read further the name of the mcu and went straight to that piece reread oh so many times in the last months... :)

Glad you got it working.

Jan

John Hite · ‎2017-03-20

Posted on March 20, 2017 at 20:40

That's all good now. I am just hoping you will look at my next timer problem I just posted.

JH