Timer behaviour after wakeup from STOP

[avidroneg]

I've searched and not found anything describing this behaviour (on the internet or this forum, which I've found to be an incredible resource so far - thank you).

I have a configuration where I go into STOP, exit out of STOP via EXTI, start TIM1, allow the stack to unwind to leave HAL_PWR_EnterSTOPMode(), and then SLEEP. With this sequence, I expect a TIM1 interrupt but never hear one.

Conversely, if I enter SLEEP instead of STOP for the very first step but perform all of the other steps identically, I get the behaviour I'm looking for - an EXTI, then a period asleep, then a TIM1 callback. This tells me that the STOP is interfering with the configuration of the timer somehow, in a way that I haven't been able to figure out how to recover from.

I've tried, after exiting STOP, to re-issue a call to HAL_TIM_Base_MspInit and MX_TIM1_Init but this has not helped. Removing the final SLEEP and spin-waiting has also not helped.

Why might this be happening? Where should I start the debug effort?

[waclawek.jan]

Gated mode of the slave-mode controller? What is the input to the slave-mode controller, i.e. what is connected to TIMx_CH1? Isn't that signal/gating the source of delay?

I repeat, output PWM by the timer, in that way you'll see if it's running or not. A very good test would be to set that timer to output PWM with PSC=0, ARR=1, CCRx=1 (i.e. toggling the output at every timer cycle) and observe.

JW

[avidroneg]

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@waclawek.jan wrote:

Gated mode of the slave-mode controller? What is the input to the slave-mode controller, i.e. what is connected to TIMx_CH1? Isn't that signal/gating the source of delay?

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The gate function is working fine and I don't think is the source of the problem. It is tied to PA8. PA8 successfully ungates the timer both before and after STOP; the problem is that the necessary ungated duration to interrupt grows significantly after the STOP, so I still suspect timer clock configuration of the kind that @carlbidwell has described.

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output PWM by the timer, in that way you'll see if it's running or not. A very good test would be to set that timer to output PWM with PSC=0, ARR=1, CCRx=1 (i.e. toggling the output at every timer cycle) and observe.

I will try that when I have an opportunity; thanks.

[Gyessine]

Hello @avidroneg 
Did you try to measure the delay and does the delay get affected by changes in the frequency supplied to the timer or other factors?
It would be helpful if you could provide more details, such as a capture from a logic analyzer or oscilloscope.
Additionally, did you refer to the "slave mode: Gated mode" in section 20.3.25, "Timer synchronization," in the reference manual.
BR
Gyessine