The DMA impact of SPI on ETH in STM32H7

[ketlen]

Hi All.

In STM32H743, if ICache is enabled and DCache is turned off, SPI frequently uses DMA to transfer data(SPI transmission interval is within 10ms), and ETH may experience transmission lag; If ICache and DCache are turned off, there is no problem with ETH transmission. Through testing, it was found that the Ethernet took more than 1 second to complete the transmission process, with Ethernet typically completing the transmission in around 10 microseconds. From the manual, it was found that ETH's DMA is a dedicated DMA and should not be affected by DMA1 and DMA2. Why?

The time consumption of using pin testing is to set the pin to low level after sending, and to high level after sending is completed.

The abnormal waveform captured by the oscilloscope is as follows:

The low level of the pin indicates the time taken from sending to completion of sending.

Thanks so much for helping out

[STea]

Hello  @ketlen ,

I think the method you are using to measure the time of the transmission can be the issue as your context can be interrupted by other interrupt sources while the io is still pulled high, so I think you are not measuring the right timing of transmission. you can investigate your call stack to see for sure if it is the case.

I don't see a direct relation with Ethernet DMA and SPI or any other peripheral using DMA1 or DMA2.

the only think that could happen is corrupting the Descriptors and buffers of ethernet in RAM when writing in the same space but I don't think this is your case as corrupting them renders the ethernet unusable and not slowing down.

BR