the adc result in dual mode are not in the right order

[H.Darwish]

hello

i am using stm32f103 for reading a 10 adc channels and i am using Dual mode regular simultaneous with DMA , the result are loaded in a buffer.

the problem is the loaded data from the ADC1 are in the right order (1st data is from 1st channel)

but the data from ADC2 are in the right sequence , for example : the last register in the buffer array is corresponding to the rank 3 of ADC2

how i can fix this

[Tesla DeLorean]

My recollection with the F1+SPL is that I configured DMA in 32-bit wide mode and read the ADC CDR (Common Data Register)

I'm afraid I can't analyze CubeMX/HAL code in an unpaid capacity.