cancel
Showing results for 
Search instead for 
Did you mean: 

SysTick Timer Configuration

Lucifer37
Associate III

How to configure the sysTick_Handler(), when we are setting the HCLK 386MHz in CubeMX and systemClock() is generated, but while configuring sysTick(), 

uint32_t SystemCoreClock = 64000000; already there in system_stm32h7xx_dualcore_boot_cm7_cm4.c

(void)SysTick_Config((SystemCoreClock) / 10000);

Will it effect mine overall MCU speed and performance, because after all I'm using FMC NAND Flash to communicate with the external Micron Flash, because there I need to calculate the clock cycles need to the write enable (WE), Setup time, Address Latch Enable (ALE) time etc, will be effected, or it is completely independent, should I only consider FMC_CLK which is coming from PLL clock source 2.

1 ACCEPTED SOLUTION

Accepted Solutions
mƎALLEm
ST Employee

Hello,

Not sure what do you want to do! Have you the intention to measure all these timings with system tick timer i.e.  the WE, Setup time, ALE time? if yes I don't know how you plan to do so!

Meanwhile, FMC kernel clock can be derived from the following clock sources:

screenshot.png

While the system tick clock is derived from the system clock source:

screenshot.png

To give better visibility on the answered topics, please click on "Accept as Solution" on the reply which solved your issue or answered your question.

View solution in original post

4 REPLIES 4
TDK
Super User

Clock cycles of the FMC are independent of SysTicks. You should only consider the frequency of the FMC clock.

If you feel a post has answered your question, please click "Accept as Solution".
mƎALLEm
ST Employee

Hello,

Not sure what do you want to do! Have you the intention to measure all these timings with system tick timer i.e.  the WE, Setup time, ALE time? if yes I don't know how you plan to do so!

Meanwhile, FMC kernel clock can be derived from the following clock sources:

screenshot.png

While the system tick clock is derived from the system clock source:

screenshot.png

To give better visibility on the answered topics, please click on "Accept as Solution" on the reply which solved your issue or answered your question.
Lucifer37
Associate III

Hi,

@mƎALLEm @TDK 

I took reference from this knowledge notes for calulate the timing / cycles for my MT29F1280AJAAA (I'm using STM32H745ZIT3) In Asynchronous mode - 5, which is saying ~50Mhz in the datasheet. But I'm running FMC at 131MHz clcok, what ever the calculation I have calculated are as per this knowledge notes, 

https://community.st.com/t5/stm32-mcus/how-to-configure-the-fmc-peripheral-to-interface-an-stm32-mcu/ta-p/705805

So help me debug the issue using CRO hardware or Software timing calculation, What I'm observing is that in middle some pages data integrity is failing, after writing page 25m sec delay I'm reading back. its failing what ever the content I have written on to that page.

My calculations, I also tried changing values by incrementing then, last or first byte is coming 0xFF

TCLRSETUPTIME = 3
TARSETUPTIME = 3

STEUPTIME = 2
WAITSETUOTIME = 3
HOLDSETUPTIME = 2
HIZSETUPTIME = 4

Question : Is Common space timing and Attribute space timing should be same  or diffrent, whats the significance of it ?

please help me find out the issue.

Hello,

This is a new question. 

Please make sure to ask one question per thread. Your original question was about measuring the timings using system tick timer. Your new question is about how to configure the memory interface and memory data integrity issue.

To give better visibility on the answered topics, please click on "Accept as Solution" on the reply which solved your issue or answered your question.