System clock switching

[MikeDB]

My STMF103 user interface processor needs two modes of operation. One needs to be as fast as possible updating the TFT or TX/RX data, and the other can be slower when it is just monitoring keys and switches. To save power I was thus thinking of using an 8MHz crystal and setting the Clock Configuration Register PLLMUL to *16 and PLXTPRE to 1 which I think gives a main clock of 4 MHz and a PLL clock of 64 MHz. Then I would use the same register's System Clock Switch bits to switch between PLL (10) and HSE(01) to give a Fast and Slow mode.

My question is can this be done seamlessly in the processor possibly every second or two without the processor having some noticeable dead time during switching ?

Also are 4 MHz and 64 MHz the greatest difference I can achieve as I assume I can't turn the PLLXTPRE on and off as it will disturb the PLL ? Even a 1MHz clock would be more than enough to monitor the input switches, but as the processor does the switch scanning it can't be put in sleep mode.

Obviously I will also optimise the peripheral clocks once this is sorted to minimize power as well. I'm not using USB so no need for a reliable 48MHz clock.

[Jack Peacock_2 · Accepted solution]

No reason you can't switch between HSE and PLL as SYSCLK source, as long as you leave the PLL running (which consumes significant power). You will have to be clever with the PCLK dividers to keep the peripheral clocks constant. Use /1 at 4MHz, and /16 at 64MHz (not sure if the F1 can divide that high), plus take into account APB and AHB limitations, which will sharply limit how fast you can run a timer, run DMA transfers, USART baud rate, etc.

Jack Peacock

[Piranha]

You can also divide AHB clock, but keep in mind that CPU core (HCLK) runs from AHB clock not SYSCLK.