SYSCLOCK configuration problem on STM32F100VE

[VCedr.1]

Hello,

I have a software that has been working

fine for several years on a STM32F100VCT6. However, today we are trying to use this

software on the MCUs ref: 100VDT6 or 100VET6.

On these 2 new references no programming problem with the same binary file. On the 100VD everything works fine too, but on the 100VE there are problems.

After analysis, the problem comes from the initialization of the CPU clock. In our application, we use an external oscillator 8Mhz and configure the PLL to have SYSCLK=24MHz. (PREDIV1 ="/2" and PLLMUL="x6")

On the VC and VD the SystemCoreClock returns =24MHz, but on the VE SystemCoreClock returns =48MHz however it is not possible on this MCU: the max is 24MHz so that's why it does not work.

I checked the RCC registers after the same initialization phase:

-        On the VC and VD ref, I have     CFGR= 0x0013000A          CFGR2=0x00000001

-        On the VE ref, I have                  CFGR= 0x0011000A          CFGR2=0x00000000

it seems that the writing to the CFGR2/PREDIV1 bits or PLLXTPRE bit doesn’t work on the 100VE ref. Why?

I am very surprise of this behavior because these 3 MCUs are from the same family: STM312F1 Value Line, so the same core and same peripherals, only the flash and ram size should be different.

To be sure, I tried creating a new project with the latest version of the ST library to verify the problem doesn’t come from my old versions of files. I used STMCubeMX and created a new empty project for the STM32F100VE with the same clock configuration but no changes, it also doesn’t works. I have the same observations CFGR2/PREDIV1 bits or PLLXTPRE bit are not written.

Do you have any idea why I have this behavior and if this issue is already known on this MCU reference?

Do you have any idea how to configure the RCC registers to have compatibility between these 3 references?

Thanks for help.

[STOne-32]

Hi,

Is that possible to have the The REV_ID bits in the DBGMCU_IDCODE for these 3 MCUs, it may happen that one of them is not from the optimized silicon or the opposite here is the Errata of the STM32F100-C/D/E RevA which is the same silicon : https://www.st.com/resource/en/errata_sheet/cd00288116-stm32f100xc-stm32f100xd-and-stm32f100xe-highdensity-value-line-device-limitations-stmicroelectronics.pdf so the behavior above is very surprising indeed. It may happen also that the Generated code is using a wrong define and so configuring the PLL output to 48MHz which is for F103VE instead ( 512K of Flash).

Hope it helps you @Amel NASRI​  .

Cheers,

STOne-32.

[Amel NASRI]

Hi @VCedr.1​ ,

Besides to what was already asked/suggested by @STOne-32​ , could you please try this configuration: "PREDIV1 = /1" and "PLLMUL = x3" with HSE as input clock in order to reach the 24 MHz? Does it work for the 3 references as expected?

-Amel