2020-05-13 04:39 PM
I'm really struggling with this problem. This is my first time trying to do anything low power, so please forgive any noob mistakes. All I'm trying to do is get the hang of a simple low power program so I can apply it to a larger one. My code is here: https://pastebin.com/zF5aPFGk
It's literally just about as simple as it can get, I've tried various combinations of commenting and uncommenting different functions (you'll notice some things like SYSCLKConfig_STOP(); commented out, but don't worry, it's been tried). It's just running on the 4MHz MSI default clock, with a 32.768kHz LSE connected to the RTC and LPUART
All the code should do is:
Yet I kept getting random hardfaults. Eventually after days of debugging I've tracked it down to the stack becoming utter garbage as soon as it wakes up from STOP2 mode. Is there something I'm doing wrong here?
Stack before wfi instruction executes:
x/16xw $sp
0x2009ffc8: 0xc0ffffff 0x01000050 0x2009ffd8 0x2009ffd8
0x2009ffd8: 0xe000ed00 0x0000ffff 0x00000003 0x00000000
0x2009ffe8: 0x080001e5 0x0800550d 0x00000000 0x00000000
0x2009fff8: 0x00000000 0x08000c43 Cannot access memory at address 0x200a0000
Stack right as it enters the interrupt handler:
x/32xw $sp
0x2009ffa8: 0x00000001 0x00000001 0xe000ed00 0x00000001
0x2009ffb8: 0x00000000 0x080005f3 0x0800177e 0x61000000
0x2009ffc8: 0xe6513c6c 0xcae0959a 0x146f5b2a 0x33be356b
0x2009ffd8: 0x946b4f6f 0xeffaf2a7 0x64f8966b 0xcf7200b6
0x2009ffe8: 0x72fd85f8 0x7ff9767b 0x73b6792c 0x71f1f879
0x2009fff8: 0x1c961ccf 0xfcfbce38 Cannot access memory at address 0x200a0000
I'm also quite unsure how the stack is getting pushed up between the wfi and the first instruction of the interrupt handler, but if someone would like to look at the assembly or just knows why, I'd greatly appreciate it.
Assembly/list file is attached
Solved! Go to Solution.
2020-05-14 02:12 AM
RM0432 Rev 6 , 5.3 Low-power modes:
Stop 2 mode with SRAM3 content lost when the RRSTP bit is cleared in PWR_CR1 register (default setting).
JW
2020-05-14 02:12 AM
RM0432 Rev 6 , 5.3 Low-power modes:
Stop 2 mode with SRAM3 content lost when the RRSTP bit is cleared in PWR_CR1 register (default setting).
JW
2020-05-14 08:55 AM
Thank you so much! I had been reading though RM0432, but missed that one part. Everywhere else (even a few lines above that quote) says that SRAM3 content is preserved in STOP2 mode. I should've looked harder! Thanks again :grinning_face: