Hi all,
i am going through deeper configuration of GPDMA on STM32U5 and there are some things i do not understand.
S/DBL_1 in TR1 register is able to vrite destination/source burst length in range 0-63 but FIFO size is 8 bytes for channels 0-11 and 32bytes for channels 12-15. Why is burst length possible to set up up to 64? How is GPDMA able to buffer that into FIFO? Isnt it a mistake in RM0456?
