STM32U5 Burst length vs FIFO size

[Eiffel]

Hi all,

i am going through deeper configuration of GPDMA on STM32U5 and there are some things i do not understand.

S/DBL_1 in TR1 register is able to vrite destination/source burst length in range 0-63 but FIFO size is 8 bytes for channels 0-11 and 32bytes for channels 12-15. Why is burst length possible to set up up to 64? How is GPDMA able to buffer that into FIFO? Isnt it a mistake in RM0456?

[AScha.3]

Hi,

why mistake ?

- one is the capability of the DMA , burst settings

- other is the FIFO size

So you can set the burst to be smaller or fit the fifo size, but also make big bursts, if you need this,

no matter, it will be all in fifo or not.

Up to you, to choose the optimum setting for a certain application/use case.

[Eiffel]

I am sorry but what? 

Burst transfer is not based on FIFO? Then how do you activate using FIFO? How do you configure FIFO? How do you want to configure different burst count of source and destination? 

[AScha.3]

from rm:

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>Burst transfer is not based on FIFO?

No. You can transfer lets say, from mem to mem, in burst - using no fifo.

Its not only about speed: the DMA is a state machine and will do a transfer always in max. speed .

The problem is more the bus : every transfer uses the bus and so only ONE , cpu or dma or other dma, can heve the bus for a transfer, all others have to wait. So if you doing a burst transfer, bus is busy for some time.

Now think: what happens if this for some reason happens more often than you think? The bus is busy for almost 100% of time and the cpu is waiting...

I had this on a machine, the dma transfer in a burst, but depending on the working frequency of a timer; seems working fine, but then the timer needed to work at a somewhat higher frequency - and suddenly the whole system was in "slow motion" , even "Stop" needed 30 secs or so to stop the machine, a catastrophic behavior.

So the programmer was not aware of the bus is busy with every transfer and this could be the end of the intended behaviour of the machine, if the frequency just gets a little bit higher (than he had tested it ).

So using burst or fifo or both depends on the use case. And its a complex game, no simple standard solution.