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STM32U5 ADC1 : does conversion time depend on sampling time configuration ?

PatriceL
Associate II

Hi,

 

I'm working on ADC1, on a STM32U5 (on a Nucleo  board). In reference manual (RM0456) § 33.4.13 "Channel-wise programmable sampling time" we can read how to compute the total conversion time Tconv.

 

The example is given for SMP = 5 ADC clock, at 55Mhz. It says:

PatriceL_1-1721994741739.png

 

What I need is a confirmation about the statement I stressed in pink on the above picture "for 14-bit mode".

Does it mean that if I set ADC1 to 12 bits or 10 bits resolution the computation is not done with 17 cycles but with something else (less than 17) ?

Said differently: does the number of ADC clock for the conversion depends on the ADC resolution or is it fixed at 17 cycles for ADC1 ?

My guess is that sampling time is programmable but conversion time is fixed whatever the resolution. Since in the RM I do not find any list of conversion time I tend to conclude I'm correct.

 

But I'd like a confirmation to this.

Best regards

Patrice.

 

 

 

 

1 ACCEPTED SOLUTION

Accepted Solutions
STOne-32
ST Employee

Dear @PatriceL ,

 

First thanks for the interesting question that the answer should be clearly mentioned in our Reference Manual but it seems not so straightforward.

 

May be the answer is here https://www.st.com/content/ccc/resource/training/technical/product_training/group1/2a/84/42/de/d3/72/44/87/STM32U5-Analog-ADC-DAC_ADC-DAC/files/STM32U5-Analog-ADC-DAC_ADC-DAC.pdf/_jcr_content/translations/en.STM32U5-Analog-ADC-DAC_ADC-DAC.pdf

Page 6 and especially Page 16 . Basically at documentation level we handle common chapters in English to describe different ADCs having some more or less features :

 

Sampling time is fully configurable as you shown above . but Conversion is fixed depending on the 12 or 14-bits selection : 12,5 cycles  and 17 cycles respectively when sampling is over and starts converting.

 

Let me know if it helps you .

by the way we need to fix this material ( remove target and red ) Merci et bien à vous 

Ciao

STOne-32

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3 REPLIES 3
STOne-32
ST Employee

Dear @PatriceL ,

 

First thanks for the interesting question that the answer should be clearly mentioned in our Reference Manual but it seems not so straightforward.

 

May be the answer is here https://www.st.com/content/ccc/resource/training/technical/product_training/group1/2a/84/42/de/d3/72/44/87/STM32U5-Analog-ADC-DAC_ADC-DAC/files/STM32U5-Analog-ADC-DAC_ADC-DAC.pdf/_jcr_content/translations/en.STM32U5-Analog-ADC-DAC_ADC-DAC.pdf

Page 6 and especially Page 16 . Basically at documentation level we handle common chapters in English to describe different ADCs having some more or less features :

 

Sampling time is fully configurable as you shown above . but Conversion is fixed depending on the 12 or 14-bits selection : 12,5 cycles  and 17 cycles respectively when sampling is over and starts converting.

 

Let me know if it helps you .

by the way we need to fix this material ( remove target and red ) Merci et bien à vous 

Ciao

STOne-32

Hi @STOne-32  and thank you for the confirmation. I've already read this pdf you mention, but did not pay enough attention to the table on page 16.

So, this conversion time is fixed in number of clock, what is confusing is the sentences "for 14 bit" for ADC12 and "for 12 bit" for ADC4 that appears also on the slide 16: Maybe I'm overthinking, that's my thing, but such a statement could be interpreted as "so if not 14 bits the conversion time is not 17 clocks but something else but we do not say how many "

 

Thank you for the answer.

Patrice

Thanks for sharing and inputs . Just for fun - it might be French/ italien style  translation to English in our Manuals . have a great day ! And good time this evening with the opening ceremony.

Ciao

STOne-32