STM32L5xx OctoSPI Read/Write to Xilinx FPGA Configuration Using SelectMAP

[CMcCa.1]

Hi. I want to use the OctoSPI to configure Xilinx FPGAs (e.g., Kintex-7) in the SelectMAP mode. Therefore I need 8 data bits, a chip select (CSn), a RD/nWR signal and a CLK to the FPGA. I know the OctoSPI is usually used for reading and writing to QSPI or Octo-Flash memories, which have instruction commands that are passed to the Flash before the actual data transfer occurs. In the case of the Xilinx SelectMAP, it’s more like a FIFO where I just need to set the RD/nWR low (write mode), along with chip select low, then just <write><write><write>…<write> a total of 16 MBytes of data. Conversely, if I wants to read back the FPGA configuration I set the RD/nWR high (read mode), assert CSn low, then just <read><read><read>…<read> all of the 16 MBytes of data back.

Based on the information I’ve read in the STM5L-Series Reference Manual (RM0438), it looks like I may do this in either Indirect- or Memory-Mapped-Mode.  So I have four questions:

1. Is this possible, to just write (or read) a block of data out of the OctoSPI port without the addition of instructions or commands prior or during the block of data transfer?

2. Is the SPI_DQS used as the RD/nWR signal, or would this be a separate GPIO?

3. Can I use the MCU's DMA engine to do this transfer?

4. Do you have example C-code (or pseudo code) that goes over the OctoSPI configuration and process I would use?

Thanks!

[Andreas Bolsch]

Before doing anything else I'd strongly recommend to read the errata sheet carefully. The OctoSpi has quite a lot of bugs/limitations, maybe not of serious concern for ordinary flash memories, but in you application ... In particular regarding DQS requirement.

If octo mode is not possible in your case due to these limitations, you might consider dual quad mode instead, this way you still get 8 bits per clock or edge, except that the nibbles would have to be rearranged before or after the transfer.