GPIOs are exactly that - General Purpose. They're not usually fully fully characterized for High-Speed design (unlike transceivers). It's possible that their output impedance is not even consistent enough to specify.
> ST's L4 series has rising and falling edges of less than 1 ns.
Actually, based on the datasheet's "Output timing characteristic", with the GPIOs at their default speed (set after reset), the rise-time is 17ns-25ns depending on CL and VCC. [UPDATE: this is wrong. the numbers I quoted are the MAX rise-time, which is not helpful]
It's an interesting question, whether the "connectivity" (UART,SPI) peripherals make use of the GPIO buffers (*), or if the alternate function actually connects the pin to something else? I don't know the answer to that, but my guess is they just use the GPIO buffers. As @AScha.3 pointed out, those GPIO ports can be configured for different speeds. At reset they are set to the lowest speed. At the highest speed, with a small load, they can reach get down to 1.8ns (which *is* surprisingly fast).
So, just use lower speeds. No one would use a UART for "Ludicrous Speed", and even at the higher end of where you would use a UART, say 8mbps, the clock period is still a comfy 125ns. async UARTs are purpose-built to sample half-way through a clock-period, so the slowest rise-time should be fine for typical loads. But that's SI, not EMI.
> The high-performance series clock goes beyond 400 MHz.
But that's irrelevant here. That's the internal clock generated by the PLL which feeds the processor and internal busses,
it does not dictate the rise-time of the output buffers which drive signals off-chip.
> I already found the GPIO capacitance (~5pF). If I also had the inductance, it would be enough to calculate.
I'm pretty sure what the data sheet calls "I/O capacitance = 5pf" is actually just input capacitance at the (GP)I/O pin, and this won't help you at all with output impedance (driver output capacitance? I'm not sure that's even a thing in datasheets).
It doesn't even matter for input impedance. Since you're using series-termination (AKA reflected-wave termination), you must be assuming that the input impedance is very high (as well you should, the input is most likely the gate of a FET)
It wouldn't hurt to do is a simulation with the IBIS files ST provides. For one thing, they can help you decide on the size of your series termination, if you think you need one.
Since you specifically mention EMI ( rather than SI concerns), can you tell us more about the requirements you're designing for? is your board going to be tested for regulatory EMC compliance? are you sure what you're worried about is even an issue?
(*) Late Update:
My question is answered in
http://efton.sk/STM32/gotcha/g14.html
"the same set of transistors drives the output when set to GPIO Out and when set to Alternate Function (in GPIOx_MODER), if some peripheral is set to output a waveform of given frequency (e.g. Timer outputting PWM), this parameter ensures that with appropriate setting of GPIOx_OSPEEDR the given frequency is attainable."
So, the GPIO speed settings do also control the edge rate of the SPI, as I guessed.
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