2018-03-13 09:20 AM
Using the Nucleo-L476RG development board for code development for a design prototype. What is the expected linear range of the DAC?
For the linear range, I am measuring the lower bound of the DAC about 55mV and upper bound about 3.271V.
Below and above this range the DAC rails. Vref (pin AVDD) is measured at 3.3191V.
This testing implies that the usable DAC range is approximately 70 counts to 4030 counts with resolution of 0.81mV/cnt (i.e. 3.319/4096 ... or 0.806mV/cnt if 3.3/4096), no?
If I execute the 'ADC_SingleConversion_TriggerSW_IT' program, the following DAC values are used (per comments in code)
/* Set DAC output on 5 voltage levels, successively to: */
/* - minimum of full range (0 <=> ground 0V) */
/* - 1/4 of full range (4095 <=> Vdda=3.3V): 1023 <=> 0.825V */
/* - 1/2 of full range (4095 <=> Vdda=3.3V): 2048 <=> 1.65V */
/* - 3/4 of full range (4095 <=> Vdda=3.3V): 3071 <=> 2.475V */
/* - maximum of full range (4095 <=> Vdda=3.3V) */
What I obtain:
DAC CNT|uhADCxConvertedData|uhADCxConvertedData_Voltage_mVolt|Measured DAC (LeCroy)
0 | 0 | 0V | 55.4mV
1023 | 983 | 793mV | 850mV
2048 | 2011 | 1.619V | 1.680V
3071 | 3035 | 2.444V | 2.500V
4095 | 3994 | 3.218V | 3.271V
The calculated DAC voltage (from ADC) is approx 56mV in error compared to measured DAC voltage.
Is this an offset within the ADC and can this be calibrated out internally via HAL/MIX/LL calls or do I have to write an ADC calibration routine?
Issue: I am doing motor control and need to use an external Vref as a basis. The offsets in the DAC and ADC need to be calibrated out and the linear range of each conversion (DAC and ADC) is required
#stm32l476-dac #stm32l476-adc2018-03-13 11:03 AM
What is the DAC load? DAC output buffer is on? Do your results depart from what's given in the DAC characteristics table in DS?
ADC offset is supposed to be nulled by calibration to be performed before first conversion, see Calibration (ADCAL, ADCALDIF, ADC_CALFACT) subchapter of ADC chapter in RM.
JW
2018-03-13 12:32 PM
ADC_SingleConversion_TriggerSW_IT example provided in en.stm32cubel4.zip
No load on the DAC - developing code at this moment. In the application, the DAC will be connected to an analog input of an H-Bridge. The analog
input is used for the PWM control of the current loop. Need to monitor Vref of the H-Bridge via ADC to eliminate any offsets going into the comparator of the PWM control section. On the Nucleo-L476RG board, I removed SB21 so the LED is not loading the buffered output of DAC2In the
ADC_SingleConversion_TriggerSW_IT
example, DAC output buffer is enabled and thebuffer
is railing. Would like to know what are considered typical margins that I need to include. Per spec, it gives 200mV for each rail (200mV -> 3.1mV) at 25C I assume. To insure a 4-sigma that the DAC output is not hitting abuffer
rail (min/max limit) is 200mV sufficient??/* Configuration of DAC channel */
sConfig.DAC_Trigger = DAC_TRIGGER_NONE;
sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
From Spec:
VDAC_OUT - Voltage on DAC_OUT output:
DAC output buffer ON: (min) 0.2, (max) VREF+ – 0.2 V
DAC output buffer OFF: (min) 0, (max) VREF+In the example, the ADC is internally connected to the DAC. Is the ADC connected before or after the buffer? It appears after the buffer
The
ADC_SingleConversion_TriggerSW_IT
example does not perform an ADC calibration. HAL_ADCEx_Calibration_Start() is no where to be found in the example's project. I'll add HAL_ADCEx_Calibration_Start() to the example and use HAL_ADCEx_Calibration_GetValue() to see what offset was calculated and if this improves the ADC values obtained.For the DAC values of 1023, 2048 and 3071 and AVDD = 3.319, the DAC outputs should be 0.829V, 1.66V and 2.49V. I measured 0.850V, 1.68V and 2.50V respectively. Some offset at lower DAC values that needs further investigation. Used factory DAC offset for these tests
2018-03-13 01:43 PM
Jan
For readability for those who may follow this thread, DS is for DS10198 (DocID025976 Rev 5) and RM is for RM0351, no?
2018-03-13 02:26 PM
HAL_ADCEx_Calibration_Start() to example
ADC_SingleConversion_TriggerSW_IT.
Using HAL_ADCEx_Calibration_GetValue(), the calibrated offset was 62. The results obtained below are more aligned
DAC CNT|uhADCxConvertedData|uhADCxConvertedData_Voltage_mVolt|Measured DAC (LeCroy)
0 | 50 | 40mV | 55.4mV
1023 | 1045 | 842mV | 850mV
2048 | 2073 | 1.670V | 1.680V
3071 | 3099 | 2.497V | 2.500V
4095 | 4057 | 3.269V | 3.271V
Two comments regarding User Manual UM1785 (Description of STM32F0 HAL and low-layer drivers)
On page 100 of UM1785, rev 6
7.1.2 Detailed description of functions
HAL_ADCEx_Calibration_Start Function
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start (ADC_HandleTypeDef * hadc)
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff)
ADCEx_Calibration_GetValue()'
is used in UM1785 for examples of APIs but NOdescription
block
is given for this function! The same is also true for 'HAL_
ADCEx_Calibration_SetValue()'. I grabbed the following from file stm32l4xx_hal_adc_ex.c
uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff)
HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
2018-03-14 03:05 AM
For readability for those who may follow this thread, DS is for DS10198
(
DocID025976 Rev 5) and RM is for RM0351, no?Probably yes - I am lazy to look up the numbers for your particular mcu model... ;)
Generally, these data are (or should be) in the respective datasheets and reference manual for all STM32 (although the ADC calibration applies only to some of them).
If you need some assurance for the values in the DS, I'm afraid you'd need to contact ST directly.
JW
PS. Just to make this sure: you've set the respective pin to Analog mode in GPIO and made sure pullup/pulldown is switched off - you can verify by reading back and checking the relevant GPIO registers
2018-03-14 03:17 AM
Dan,
I don't use the L4 and a brief glance at the DAC chapter in RM0351 reveals that it's way more complex than the one in the 'F4 I'm using.
Worth a thorough reading (as chapters for every other peripheral you may be using).
E.g.
In the example, the ADC is internally connected to the DAC. Is the ADC connected before or after the buffer?
is probably answered in DAC channel modes -> Normal mode (i.e. it is selectable)
JW