DAC output offset spec with output buffer enabled

[calvin]

Hi,

Currently, we are facing an accuracy problem when using the built-in DAC on the STM32F407 (with buffer enabled). As the built-in reference voltage measured 2.0005V, we set the DOR to 0x800, expecting to get 1.25V on the DAC output. However, we actually measured 1.238V, which is 122mV away from the ideal. All tests were made with the DAC under no load.

As I've seen in datasheets and many posts, the mentioned DAC output range will be 0.2V~ (VDDA-0.2V) when the buffer is enabled. Could I suspect that the DAC output offset specification is within (IDEAL ±0.2V)? Given the 122mV error mentioned above, it's hard to estimate the output accuracy without any listed specifications to refer to.

Overall, I think the built-in buffer actually works and is usable, but we really need more information about it to leverage it better.

Thanks.

[TDK]

The 0.2V~ (VDDA-0.2V) spec is the rails. It should be considerably more accurate than +/- 0.2V. In this case, +/- 12 LSB.

> As the built-in reference voltage measured 2.0005V, we set the DOR to 0x800, expecting to get 1.25V on the DAC output. However, we actually measured 1.238V, which is 122mV away from the ideal.

Not sure I follow the math here. If VREF+ is 2.005V , a 12-bit DAC output of 0x800 should be near 1.0025 V.

[calvin]

>Not sure I follow the math here. If VREF+ is 2.005V , a 12-bit DAC output of 0x800 should be near 1.0025 V.

It's my typo, and there is something that needs clarification. The voltage of VREF+ is measured at 2.5005V, and it comes from an external voltage sourced from the AD7175-2 REFOUT.

However, as it lists ±12LSB at VREF+ = 3.6V, does this mean the offset error only occurs within 12LSB when VREF+ = 3.6V? If a VREF+ voltage other than 3.6V is applied, is the error then not estimable?

I didn't actually test applying 3.6V to both VDDA and VREF+, but I tried to tie VREF+ to VDDA, which was applied with a stable voltage measured at 3.271V. This resulted in the 0x800 being 1.6201V, which should be near 3.271/2 = 1.6335V, yet there was still a 132mV error.

[waclawek.jan]

While the DS are not clear in this regard, I believe the offset/gain specs are given for the buffer off case.

How is the DAC loaded in your circuit?

JW

[TDK · Accepted solution]

2.5005 / 2 - 1.238 = 0.01225

That's an error of ~12.2mV, higher than 12 LSB, but much closer to what you should be expecting.

> However, as it lists ±12LSB at VREF+ = 3.6V, does this mean the offset error only occurs within 12LSB when VREF+ = 3.6V? If a VREF+ voltage other than 3.6V is applied, is the error then not estimable?

The datasheet tests specific conditions, but the limits should be comparable to similar setups.

> This resulted in the 0x800 being 1.6201V, which should be near 3.271/2 = 1.6335V, yet there was still a 132mV error.

You mean 13.2 mV?

A good test would be to disable the buffer, and disable any external loading, and see if the outputs fall in line with what the datasheets guarantee.

[calvin]

>> This resulted in the 0x800 being 1.6201V, which should be near 3.271/2 = 1.6335V, yet there was still a 132mV error.

>You mean 13.2 mV?

Yes, I mean it!  My poor calculation ...

In my actual case, I set the DAC to 1229, expecting to get 0.75V (VREF=2.5V). There were two boards doing the same thing; one measured 0.748V, and the other measured 0.733V, both with buffer enabled. I'm not sure if that board has a broken MCU or if it's just a variation in part quality.

In my case, the ±12LSB was calculated as a ±7.3mV potential error, but if it goes up to 17mV, how can I estimate the maximum?"

[calvin]

Hi,

For the test, the DAC output was left floating.

I also thought that the listed offset specification only applied when the buffer is off; the buffer amplifier should have a different specification.

[waclawek.jan]

> the buffer amplifier should have a different specification

I agree, and IMO as a minimum, the fact, that gain/offset is given for buffer OFF should be clearly marked in the DS.

But it is what it is.

The STM32 are a huge digital circuit with some analog functions slapped on. Few users realize that analog functionality built on what is primarily cheap digital process, is nothing short of miracle; it is actually very hard to do and full of compromises. Unfortunately, this does not show when looking at specs, which appear to be mediocre, if compared to dedicated analog devices (pun intended).

The 'F4 is relatively old, some 12 years now. If you look at newer STM32 e.g. 'L4 or 'G4, their DAC do have separate specs for buffer OFF/ON; however, their buffer opamp has a digital trim and its initial value is determined at manufacturing. That's the magic; but as all magics, it's not free - it means both silicon area, read, cost; and testing time for each individual part, read, cost.

JW

PS. How much error did you measure with buffer OFF?

[TDK]

I'd also like to see the test with the buffer off. Presumably, it should fall within the limits specified by the datasheet. Agree the datasheet is lacking specificity here, couldn't find anything else that explored this further on the F4.

[calvin]

For buffer off, all output results are quite close to the IDEAL, and there is a larger dynamic range even when the DOR setting is within 100LSB to a few LSB, without significant offsets. This suggests that the DAC itself performs quite well.

anyway, below shows a bit of test result:

VREF=2.5V

Buffer ON:

DOR	IDEAL	measured voltage	error
1024	0.625	0.612	-0.013
2048	1.250	1.238	-0.012
3072	1.875	1.864	-0.011
4095	2.500	2.490	-0.010

Buffer OFF:

DOR	IDEAL	measured voltage	error
1024	0.625	0.626	+0.001
2048	1.250	1.248	-0.002
3072	1.875	1.873	-0.002
4095	2.500	2.498	-0.002

Buffer ON:

DOR	step	IDEAL	measured	error
1024	50	0.625	0.611	-0.014
1074	50	0.656	0.642	-0.014
1124	50	0.686	0.672	-0.014
1174	50	0.717	0.703	-0.014
1224	50	0.747	0.734	-0.013
1274	50	0.778	0.764	-0.014
1324	50	0.808	0.795	-0.013
1374	50	0.839	0.825	-0.014
1424	50	0.869	0.856	-0.013
1474	50	0.900	0.887	-0.013
1524	50	0.930	0.917	-0.013
1574	50	0.961	0.948	-0.013
1624	50	0.991	0.978	-0.013
1674	50	1.022	1.009	-0.013
1724	50	1.053	1.040	-0.013
1774	50	1.083	1.070	-0.013
1824	50	1.114	1.101	-0.013
1874	50	1.144	1.131	-0.013
1924	50	1.175	1.162	-0.013
1974	50	1.205	1.192	-0.013
2024	50	1.236	1.223	-0.013