2017-05-09 06:02 AM
We are working on STM32L475 Internal Flash driver and we are facing one issue and to solve that issue i need below clarification.
Is it possible to program any Flash location twice without erase?. lets say there is one page which is currently erased. so the content of all the double word location of that page after erase is 0xFFFFFFFFFFFFFFFF. and now i program one double word location of this erased page with value 0xFFFFFFFFFFFFFFFF. so my question is 'will it be possible to program this same location with value 0xAAAAAAAAAAAAAAAA or again i have to erase this location to program? any inputs are welcomed.
Thanks in advance,
Ashwin
#stm32l475 #stm32l4-flash2017-05-10 12:46 AM
This is an interesting question!
Intuitively, writing
0xFFFFFFFFFFFFFFFF should let the memory in its erased state and allow further programming, but this is not the case.
The STM32L4 devices have an additional 8-bit of embedded ECC (Error Code Correction) for each 64-bit word of data.
In the erase state, the ECC bits are set to 0xFF.
Once you wrote the word 0xFFFFFFFFFFFFFFFF at a given address, the visible bits remains unchanged, but the ECC bits get modified, to a value different from
0x
FF due to the implemented ECC algorithm.
This will prevent any further programming at this address as the hidden ECC data is likely to need some bits to change from 0->1for the new data .
In order to program something else at the same address, you will need to perform a complete page erase...
see
http://www.st.com/resource/en/reference_manual/dm00151945.pdf
3.3.2 for details2017-05-10 06:21 AM
Hello Max,
Thanks for your reply...!!!
i got your point. so is this the same case with STM32's other series also? like STM32L1 and STM32F4.
and also do you have any idea whether Internal Flash in STM32l475 is NOR flash or NAND Flash?.
as far as i know NOR flash is byte addressable. but here in stm32l475 it is not the case.it is double word addressable.
thanks once again,
Ashwin.
2017-05-10 09:41 PM
STM32 series are based on several NVM technologies.
As a consequence there are a lot of differences regarding:
- the word size (from 16-bit to 256-bit)
- ECC implementation or not
- memory point technology
Most are based on NOR flash technology, but not all of them: the STM32L1 for example use EEPROM memory.
The NOR flash is word addressable. It is byte addressable in the specific case of a byte wide memory matrix (I mean the hardware matrix implementation on silicon, not the access signals) .
In STM32 the word size varies between series in order to adapt the memory linear read access throughput (for linear code execution) to match the maximum CPU frequency.
I recommend you have look into the specific series documentation... their FLASH memory are very different.
Of all STM32, STM32L4 and STM32H7 use the most recent technologies.
2017-05-12 02:10 AM
Hello Max,
thanks for your reply.
just one more thing i want to know is is there any possibility that we can disable ECC with some register settings.
i have gone through STM32L475 reference manual but could not find anything.
but still just want to confirm.
Thanks,
Ashwin
2017-05-12 03:50 AM
No, it is not possible to:
- disable ECC
- read the ECC bits
- read the raw data in case there is an ECC correction
2017-06-06 06:05 AM
It is possible to write a position twice (but not with your suggested values)
[tested with STM32L471, L476 and L486] - perhaps L475 behaves differently, but i don't think so!
2017-06-06 09:08 PM
This is a specific value that works.
There are probably many other combinations that works, the condition is that the new data ECC code must have more '0' than the previous data ECC code.
With the right chain of values, you may be able to do a few write before you need to erase...
2017-06-07 02:16 AM
Are you sure? (If yes, what algorithm is used?)
Zero is a special value, that have worked since STM32F1. Writing i.e. 0xFFFE, 0xFFFC, 0xFFF8, 0xFFF0, ... haven't worked with any STM32 yet. If this feature is implemented in L4, it would be very welcomed ;) Until now the flash controller blocks this type of rewriting. I would be very surprised, if it works for L4.