STM32L051: clear PWM output on COMP2 trigger.

[bart2]

Posted on August 26, 2015 at 17:32

I am quite new to STM32 and try to do my second application using an STM32L051K8T6 where I need a PWM signal that is aborted when current rises above a treshold. It didn't take me too long to get this working on the STM32F0DISCOVERY board (software development/proof of concept when the final hardware wasn't ready yet), but somehow I can't get it to work on the L

The toolchain I use is Keil uVision5 (STM Cortex M0/M0+ license), initial setup code is generated with STM32CubeMX, and I am debugging the target board through the STM32F0Discovery builtin STLink v2 interface. Little more information about the application: - I currently have all the buses and core running from the MSI oscillator at 4.194MHz. -COMP2 uses 1/4 internal VREF on the INM input and the voltage on PA3 on the INP input and is used in Fast mode. - TIM2 is used as the PWM generator in PWM mode 1 using an up counter with output inverted. Channel1 is used as PWM output exiting the chip at PA5 - When the signal on PA3 rises above 1/4 internal VREF the PWM cycle should be aborted, exacly like described in document RM0377 (STM32L0x1 reference manual) section 3.11 Results so far: - COMP2 is working; I can see bit 30 of COMP2_CSR changing and I am getting interrupts. - PWM itself is working. Signal waveforms on the scope look as expected. - PWM cycle abort is NOT working. The code used to initialise TIM2 and COMP, as generated by STM32CubeMX:

htim2.Instance = TIM2;

htim2.Init.Prescaler = 41;

htim2.Init.CounterMode = TIM_COUNTERMODE_UP;

htim2.Init.Period = 9;

htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;

HAL_TIM_Base_Init(&htim2);



sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;

HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig);



HAL_TIM_PWM_Init(&htim2);



sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;

sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;

HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig);



sConfigOC.OCMode = TIM_OCMODE_PWM1;

sConfigOC.Pulse = 9;

sConfigOC.OCPolarity = TIM_OCPOLARITY_LOW;

sConfigOC.OCFastMode = TIM_OCFAST_ENABLE;

HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1);



sClearInputConfig.ClearInputState = ENABLE;

sClearInputConfig.ClearInputSource = TIM_CLEARINPUTSOURCE_ETR;

sClearInputConfig.ClearInputPolarity = TIM_CLEARINPUTPOLARITY_NONINVERTED;

sClearInputConfig.ClearInputPrescaler = TIM_CLEARINPUTPRESCALER_DIV1;

sClearInputConfig.ClearInputFilter = 0;

HAL_TIM_ConfigOCrefClear(&htim2, &sClearInputConfig, TIM_CHANNEL_1);



HAL_TIMEx_RemapConfig(&htim2, TIM2_ETR_COMP2_OUT);

hcomp2.Instance = COMP2;

hcomp2.Init.InvertingInput = COMP_INVERTINGINPUT_1_4VREFINT;

hcomp2.Init.NonInvertingInput = COMP_NONINVERTINGINPUT_IO1;

hcomp2.Init.LPTIMConnection = COMP_LPTIMCONNECTION_DISABLED;

hcomp2.Init.OutputPol = COMP_OUTPUTPOL_NONINVERTED;

hcomp2.Init.Mode = COMP_MODE_HIGHSPEED;

hcomp2.Init.WindowMode = COMP_WINDOWMODE_DISABLED;

hcomp2.Init.TriggerMode = COMP_TRIGGERMODE_IT_RISING;

HAL_COMP_Init(&hcomp2);

Both TIM2 and COMP peripherals are started in IT mode usingHAL_COMP_Start_IT andHAL_TIM_PWM_Start_IT. When looking at the registers, I see no strange things. TIM2->CCMR1.OC1CE is enabled. TIM2->SMCR.ETPS is 0x00 TIM2->SMCR.ECE is 0 TIM2->SMCR.ETF is 0x00 TIM2->SMCR.ETP is 0 TIM2->OR.ETR_RMP is 0x06 etcetera. I also checked the code sample A.9.10 in RM0377, but that one contains an error: that sample tries to set the OCCS bit in TIM2->SMCR. This bit is not available on STM32L0x1 devices... Can anyone point me in the right direction?

[waclawek.jan]

Posted on August 26, 2015 at 18:22

And does it work if you set ETR to be connected to GPIO (and of course setting the appropriate GPIO and wiggling them from outside)?

JW

[bart2]

Posted on August 27, 2015 at 09:21

I didn't get to checking that yet. Will do that as soon as I have time, but it should be working with internal remapping too..

[Amel NASRI]

Posted on August 27, 2015 at 13:34

Hi van_hest.bartNo,

+1 for waclawek.jan suggestion. I also suggest to connect externally the COMP2 output to the configured ETR pin. Pay attention to comment the line:

HAL_TIMEx_RemapConfig(&htim2, TIM2_ETR_COMP2_OUT);

or generate appropriate code with CubeMX. Regarding the OCCS bit, I will check this error in RM0 -Mayla-

[waclawek.jan]

Posted on August 27, 2015 at 14:01

> Regarding the OCCS bit, I will check this error in RM0377.

Mayla, > Regarding the OCCS bit, I will check this error in RM0377. could you please also initiate revision of the ''clear'' portion of  ''Output stage of capture/compare channel'' figure for TIM2-TIM5 (and similar cathegory) timers (e.g. Figure 161 in RM0090 rev.10), across the UMs for all families? They contain reference to both TIMx_SMCR.OCCS bit and OCREF_CLR signal, none of which are present in most of the families. (I still maintain that the timer chapters should merged into one and the differences in variants should be highlighted directly in the RM, but I understand that ST is reluctant to undertake such a massive revision of key chapters). Jan

[bart2]

Posted on August 27, 2015 at 20:42

Unfortunately I could not use external ETR; that pin can only be mapped to PA15, which is in use on the board. 

But I found the problem. Adding this line to the STM32CubeMX generated initialisation solves the problem:htim2.Instance->SMCR |= 0x08; // OCCS bit? Reference manual only says this bit should be kept at '1'.In the reference manual RM0377 the OCCS bit is still mentioned the figure 97 on page 371.When I look at the field description of the TIMx_SMCR register (page 398), it says for bit 3: 'Reserved, must be kept at ‘1’.When I look in the STM32F051 manual, bit 3 of the TIMx_SMCR register happens to be the OCCS bit which should be at '1' to select ETRF as the clear source.... ('0' would be to use the OCREF_CLR input of the timer, which isn't available in the L051 I guess).OK, now on to the IrDA piece of the code... :)

[waclawek.jan]

Posted on August 27, 2015 at 21:05

Great catch!

RM0090 for STM32F4xx has this bit marked as ''reserved, must be kept at reset value'', with reset value 0. Somebody should try... JW

[bart2]

Posted on August 28, 2015 at 10:46

One more thing, but that shouldn't be here I guess unless ST makes the processor support packs:

The Keil System Viewer uses the wrong addresses for some of the SFR's of the L051. For example Keil thinks that the COMP2_CSR register is located at offset 0x34 instead of 0x1c. I have seen it with another register too, but I forgot which one. Not that much of an headache really; at most slightly annoying. Maybe it is even just a 'stupid user error'; as I said I am new to STM32 and Keil MDK-ARM too. 

[Amel NASRI]

Posted on August 28, 2015 at 12:06

Hi van_hest.bart,

Thanks for sharing the solution you found.Your feedback as well as Jan's ones are under review.I agree that the OCRefClear feature description has to be reviewed in our reference manuals to avoid such confusions.-Mayla-