Posted on February 15, 2018 at 20:15Can anyone help to explain the method to calculate the I2C timing register?
I am trying to come up with a value for 400KHz. I2C1 clock is from HSI16 which also has the /div4 enabled.
I am very confused by the set up times such as tSU;DAT.
The issue is that I am not reading the bytes correctly, which corresponds with the device errata
Wrong data sampling when data set-up time (tSU;DAT) is smaller than one I2CCLK period Description The I2C bus specification and user manual specifies a minimum data set-up time (tSU;DAT) at:
� 250 ns in Standard-mode,
� 100 ns in Fast-mode,
� 50 ns in Fast-mode Plus.
The I2C SDA line is not correctly sampled when tSU;DAT is smaller than one I2CCLK (I2C clock) period: the previous SDA value is sampled instead of the current one. This can result in a wrong slave address reception, a wrong received data byte, or a wrong received acknowledge bit. DocID028471 Rev 4 11/17 STM32L011x3/4 STM32L011x3/4 silicon limitations 16 Workaround Increase the I2CCLK frequency to get I2CCLK period smaller than the transmitter minimum data set-up time. Or, if it is possible, increase the transmitter minimum data set-up time.
I tried to use the value from STM32CubeMX and it did not help.
Processor: STM32L011K4
#stm32l011 #i2c
