cancel
Showing results for 
Search instead for 
Did you mean: 

STM32H755Zi-Q~How to share data between cores

CFran.1
Associate II

Currently I am just trying to share some data between cores, and right now I'm just trying to send a constant value to confirm operation.

I have this code located in a file called share.h,

typedef struct {
 
// shared data goes here
 
int16_t data;
 
}shared_data_t;

and then I have

volatile shared_data_t * const shared_data = (shared_data_t *)0x30040000;

saved in each core's main.c file.

The location is SRAM3 and according to the RM this is an optimal place to share values. It updates properly in M7, but when I check the struct in M4 it's not the same value. When googling, this was the number 1 answer, the second was the linker. I don't know where to begin with the linker, so if that is the option is there any good guides? Thank you for reading this

1 ACCEPTED SOLUTION

Accepted Solutions
Amel NASRI
ST Employee

Hi @CFran.1​ ,

The application note AN5617  STM32H745/755 and STM32H747/757 lines inter-processor communications is meant for use-cases as yours.

It provides an overview of the dual-core communication technique & introduces the inter-processor communication channels such as OpenAMP, RPMsg, FreeRTOS as well as the message buffer and custom communication mechanism (with some code snippets).

This is a new document, don't hesitate to share with us any feedback about its content.

-Amel

PS: Once your question is answered, please click on "Select as Best" for the comment containing the answer to your initial question.

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.

View solution in original post

4 REPLIES 4

volatile isn't sufficient for cache coherency.

Perhaps use the MPU memory settings, fencing instructions, or Clean DCache type functionality to ensure the memory is consistent.

There is also the HSEM peripheral

Tips, Buy me a coffee, or three.. PayPal Venmo
Up vote any posts that you find helpful, it shows what's working..

Thank you for the reply. I am currently using HSEM

//M7 Main File
while(HAL_HSEM_FastTake(HSEM_ID_0)){}
shared_data->data = 0x69;
HAL_HSEM_Release(HSEM_ID_0, PID_ID_0);
//M4 Main File
while(HAL_HSEM_FastTake(HSEM_ID_0)){}
 
HAL_HSEM_Release(HSEM_ID_0, PID_ID_0);

I use a breakpoint at the M4 HSEM_Rlease to ensure the M7 is polling.

When I'm in the breakpoint, I'm using the debugger watch-variable to watch shared_data->data in the M4 file

I came across the https://www.st.com/resource/en/application_note/dm00272913-level-1-cache-on-stm32f7-series-and-stm32h7-series-stmicroelectronics.pdf, and it makes sense why my data is getting stuck in the D-cache. Thank you!

Amel NASRI
ST Employee

Hi @CFran.1​ ,

The application note AN5617  STM32H745/755 and STM32H747/757 lines inter-processor communications is meant for use-cases as yours.

It provides an overview of the dual-core communication technique & introduces the inter-processor communication channels such as OpenAMP, RPMsg, FreeRTOS as well as the message buffer and custom communication mechanism (with some code snippets).

This is a new document, don't hesitate to share with us any feedback about its content.

-Amel

PS: Once your question is answered, please click on "Select as Best" for the comment containing the answer to your initial question.

To give better visibility on the answered topics, please click on Accept as Solution on the reply which solved your issue or answered your question.